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參數(shù)資料
| 型號(hào)： | MC68HC901FNR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 42/73頁(yè) |
| 文件大小： | 274K |
| 代理商： | MC68HC901FNR2 |
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Universal Synchronous/Asynchronous Receiver-Transmitter
7-4
MC68HC901 USER’S MANUAL
MOTOROLA
PE — Parity Enable
1 = Parity checked by receiver and parity calculated and inserted during data
transmission.
0 = No parity check and no parity bit computed for transmission.
E/O — Even/Odd Parity
1 = Even parity is selected.
0 = Odd parity is selected.
Bit 0 — Reserved by Motorola
This bit is reserved and returns a zero when read.
7.1.4 USART Data Register (UDR)
This register is used to either provide the current data word in the receiver buffer or to
provide data to the transmitter buffer.
D7-D0 — Data
0 = Cleared.
1 = Set.
7.2 RECEIVER
As data is received on the serial input line (SI), it is clocked into an internal 8-bit shift register
until the specified number of data bits have been assembled. The character will then be
transferred to the receive buffer, assuming that the last word in the receive buffer has been
read. This transfer will set the buffer full bit in the receiver status register (RSR) and produce
a buffer full interrupt to the processor, assuming this interrupt has been enabled.
Reading the receive buffer satisfies the buffer full condition and allows a new data word to
be transferred to the receive buffer when it is assembled. The receive buffer is accessed by
reading the USART data register (UDR). The UDR is simply an 8-bit data register used when
transferring data between the MFP and the CPU.
Each time a word is transferred to the receive buffer, its status information is latched into the
receiver status register (RSR). The RSR is not updated again until the data word in the
receive buffer has been read. When a buffer full condition exists, the RSR should always be
read before the receive buffer (UDR) to maintain the correct correspondence between data
and flags. Otherwise, it is possible that after reading the UDR and prior to reading the RSR,
a new word could be received and transferred to the receive buffer. Its associated flags
would be latched into the RSR, writing over the flags for the previous data word. Thus, when
UDR REGISTER
BIT
7
6
5
4
3
2
1
0
FIELD
D7
D6
D5
D4
D3
D2
D1
D0
RESET
0
ADDR
$2F
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