參數(shù)資料
型號： MC68HC805K3DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 94/119頁
文件大?。?/td> 2870K
代理商： MC68HC805K3DW
General Release Specication
COP Watchdog Timer
MC68HC805K3 — Rev. 1.0
76
8-Bit Timer
8.4 COP Watchdog Timer
The computer operating properly (COP) watchdog timer function is
implemented on this device by using the output of the RTI circuit and
further dividing it by eight. The minimum COP reset times are listed in
If the COP circuit times out, an internal reset is generated and the reset
vector is fetched. Preventing a COP time out is done by writing a logical
zero to the COPC bit at address $03F0 as shown below. The COPR
register is shared with a user EEPROM byte. This address location is not
affected by any reset signals. Reading this location returns the user
EEPROM byte. When the COPC is cleared, only the final four bits used
to count eight RTI cycles are cleared. The COP watchdog timer can be
enabled/disabled by a mask option register bit.
8.5 Operating During Stop Mode
The timer system is cleared when going into stop mode. When STOP is
exited by an external interrupt or an external RESET, the internal
oscillator resumes, followed by a 16 or 4064 cycle internal processor
oscillator stabilization delay. The timer system counter is then cleared
and operation resumes. If the STOP instruction is disabled by mask
option register bit to create the halt mode, the effects on the timer are as
$03F0
Bit 7
6543
2
1
Bit 0
Read:
Reading $03F0 returns the contents of User EEPROM
Write:
COPC
Reset:
—————
—
0
= Unimplemented
Figure 8-4. COPR Watchdog Timer Location
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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