參數(shù)資料
型號: MC68HC805K3DW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁數(shù): 100/119頁
文件大小: 2870K
代理商: MC68HC805K3DW
General Release Specification
PEEPROM Registers
MC68HC805K3 — Rev. 1.0
Personality EEPROM
81
9.3 PEEPROM Registers
Two register locations are used to support the EEPROM array. These
are the bit select and status/control registers.
9.3.1 PEEPROM Bit Select Register (PEBSR)
The PEEPROM bit select register is located at $000E and contains the
enable signals for the rows and columns to access the bits in the
EEPROM array. The placement of these bits is shown below. The output
of this register is connected to two decoders, one for the array column
and one for the array row.
A byte in the PEEPROM is defined by the upper four bits in the 7-bit
address in the PEBSR (PEB3 through PEB6) and the bit within that byte
is defined by the lower three bits in the 7-bit address in the PEBSR
(PEB0 through PEB2). The upper bit in the PEBSR (PEB7) may be used
as a storage location. All of the bits in the PEBSR register are cleared by
reset.
Byte (Row) of PEEPROM
Bit (Column in Byte (Row)
of PEEPROM
3210
2
1
0
$0E
Bit 7
6543
2
1
Bit 0
Read:
PEB7
PEB6
PEB5
PEB4
PEB3
PEB2
PEB1
PEB0
Write:
Reset:
00000
0
Figure 9-2. PEBSR Select Register
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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