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| 型號(hào)： | MC68HC805K3DW |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 61/119頁(yè) |
| 文件大?。?/td> | 2870K |
| 代理商： | MC68HC805K3DW |
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General Release Specication
Hardware Interrupts
MC68HC805K3 — Rev. 1.0
46
Interrupts
the external IRQ sources to be inactive if the edge- and level-sensitive
mask option register bit is selected. In this way, any additional setting
of the IRQF flag bit while in the service routine can be ignored by
clearing the IRQF flag bit just before exiting the service routine. If the
IRQF flag bit is set again while in the IRQ service routine, the CPU re-
enters the IRQ interrupt sequence unless the IRQF flag bit is cleared.
The IRQF flag bit is cleared by reset.
IRQE — IRQ Interrupt Enable
The IRQE bit enables or disables the IRQF flag bit to initiate an IRQ
interrupt sequence. If the IRQE enable bit is set, the IRQF flag bit can
generate an interrupt sequence. If the IRQE enable bit is cleared, the
IRQF flag bit cannot generate an interrupt sequence. Reset sets the
IRQE enable bit, thereby enabling IRQ interrupts once the I bit is
cleared. Execution of the STOP or WAIT instructions causes the
IRQE bit to be set to allow the external IRQ to exit these modes. In
addition, reset also sets the I bit, which masks all interrupt sources.
NOTE:
If the I bit is cleared, any instruction that sets the IRQE enable bit when
the IRQF flag bit is already set initiates an IRQ interrupt sequence
immediately after that instruction.
4.6.3 Port Interrupts (PA0–PA3)
The IRQ interrupt also can be triggered by inputs to PA0 through PA3
port pins as described in 4.6.1 External Interrupt (IRQ) if the port
interrupts mask option register bit is used. If enabled, the lower four bits
of port A can activate the IRQ interrupt function and the interrupt
operation is the same as the input to the IRQ pin. The mask option
register bit allows all of these input pins to be ORed with the input
present on the IRQ pin. All PA0 through PA3 pins must be selected as a
group and as an additional IRQ interrupt source. All the port A interrupt
sources also are controlled by the IRQE enable bit.
NOTE:
The BIH and BIL instructions apply only to the level on the IRQ pin itself
and not to the output of the logic OR gate with PA0 through PA3 pins.
The state of the individual port A pins can be checked by reading the
appropriate port A pins as inputs.
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