參數(shù)資料
型號： MC68HC711D3CP3
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 93/138頁
文件大小： 1047K
代理商： MC68HC711D3CP3
Resets, Interrupts, and Low-Power Modes
MC68HC711D3 Data Sheet, Rev. 2.1
58
Freescale Semiconductor
4.3.6 Highest Priority I Interrupt and Miscellaneous Register (HPRIO)
Four bits of this register (PSEL3–PSEL0) are used to select one of the I bit related interrupt sources and
to elevate it to the highest I bit masked position of the priority resolution circuit. In addition, four
miscellaneous system control bits are included in this register.
RBOOT — Read Bootstrap ROM
This bit can be read at any time. It can be written only in special modes (SMOD = 1). In special
bootstrap mode, it is set during reset. Reset clears it in all other modes.
1 = Bootloader ROM is enabled in the memory map at $BF00–$BFFF.
0 = Bootloader ROM is disabled and is not in the memory map.
SMOD and MDA — Special Mode Select and Mode Select A
These two bits can be read at any time.These bits reflect the status of the MODA and MODB input pins
at the rising edge of reset. SMOD may be written only in special modes. It cannot be written to a 1 after
being cleared without an interim reset. MDA may be written at any time in special modes, but only once
in normal modes. An interpretation of the values of these two bits is shown in Table 4-3.
IRVNE — Internal Read Visibility/Not E
This bit may be read at any time. It may be written once in any mode. IRVNE is set during reset in
special test mode only, and cleared by reset in the other modes.
1 = Data from internal reads is driven out on the external data bus in expanded modes.
0 = Data from internal reads is not visible on the external data bus.
As shown in the table, in single-chip and bootstrap modes IRVNE determines whether the E clock is
driven out or forced low.
1 = E pin driven low
0 = E clock driven out of the chip
Address:
$003C
Bit 7
654321
Bit 0
Read:
RBOOT
SMOD
MDA
IRVNE
PSEL3
PSEL2
PSEL1
PSEL0
Write:
Reset:
Note 1
0101
1. The values of the RBOOT, SMOD, IRVNE, and MDA bits at reset depend on the
mode during initialization. Refer to Table 4-3.
Figure 4-7. Highest Priority I-Bit Interrupt
and Miscellaneous Register (HPRIO)
Table 4-3. Hardware Mode Select Summary
Inputs
Mode
Latched at Reset
MODB
MODA
SMOD
MDA
1
0
Single chip
0
1
Expanded multiplexed
0
1
0
Special bootstrap
1
0
1
Special test
1
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