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| 型號： | MC68HC711D3CP3 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 6/138頁 |
| 文件大小： | 1047K |
| 代理商： | MC68HC711D3CP3 |
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Pulse Accumulator
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
103
8.7.2 Pulse Accumulator Count Register
The 8-bit read/write pulse accumulator count register (PACNT) contains the count of external input events
at the PAI input or the accumulated count. The counter is not affected by reset and can be read or written
at any time. Counting is synchronized to the internal PH2 clock so that incrementing and reading occur
during opposite half cycles.
8.7.3 Pulse Accumulator Status and Interrupt Bits
The pulse accumulator control bits, PAOVI and PAII, PAOVF, and PAIF are located within timer registers
TMSK2 and TFLG2.
PAOVI and PAOVF — Pulse Accumulator Interrupt Enable and Overflow Flag
The PAOVF status bit is set each time the pulse accumulator count rolls over from $FF to $00. To clear
this status bit, write a 1 in the corresponding data bit position (bit 5) of the TFLG2 register. The PAOVI
control bit allows configuring the pulse accumulator overflow for polled or interrupt-driven operation
and does not affect the state of PAOVF. When PAOVI is 0, pulse accumulator overflow interrupts are
inhibited, and the system operates in a polled mode, which requires PAOVF to be polled by user
software to determine when an overflow has occurred. When the PAOVI control bit is set, a hardware
interrupt request is generated each time PAOVF is set. Before leaving the interrupt service routine,
software must clear PAOVF by writing to the TFLG2 register.
PAII and PAIF — Pulse Accumulator Input Edge Interrupt Enable and Flag
The PAIF status bit is automatically set each time a selected edge is detected at the PA7/PAI/OC1 pin.
To clear this status bit, write to the TFLG2 register with a 1 in the corresponding data bit position (bit
4). The PAII control bit allows configuring the pulse accumulator input edge detect for polled or
interrupt-driven operation but does not affect setting or clearing the PAIF bit. When PAII is 0, pulse
accumulator input interrupts are inhibited, and the system operates in a polled mode. In this mode, the
PAIF bit must be polled by user software to determine when an edge has occurred. When the PAII
control bit is set, a hardware interrupt request is generated each time PAIF is set. Before leaving the
interrupt service routine, software must clear PAIF by writing to the TFLG register.
Address:
$0027
Bit 7
654321
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
Figure 8-21. Pulse Accumulator Count Register (PACNT)
Address:
$0024
Bit 7
654321
Bit 0
Read:
TOI
RTII
PAOVI
PAII
0
PR1
PR0
Write:
Reset:
00000000
Figure 8-22. Timer Interrupt Mask 2 Register (TMSK2)
Address:
$0025
Bit 7
654321
Bit 0
Read:
TOF
RTIF
PAOVF
PAIF
0000
Write:
Reset:
00000000
Figure 8-23. Timer Interrupt Flag 2 Register (TFLG2)
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