參數(shù)資料
型號： MC68HC711D3CP3
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 47/138頁
文件大?。?/td> 1047K
代理商： MC68HC711D3CP3
General Description
MC68HC711D3 Data Sheet, Rev. 2.1
16
Freescale Semiconductor
Figure 1-4. Pin Assignments for 44-Pin QFP
1.5 Power Supply (VDD, VSS, and EVSS)
Power is supplied to the MCU through VDD and VSS. VDD is the power supply (+5 V ±10%) and VSS is
ground (0 V). EVSS, available on the 44-pin PLCC and QFP, is an additional ground pin.
1.6 Reset (RESET)
An active low bidirectional control signal, RESET, acts as an input to initialize the MCU to a known startup
state. It also acts as an open-drain output to indicate that an internal failure has been detected in either
the clock monitor or computer operating properly (COP) watchdog circuit. In addition, the state of this pin
is one of the factors governing the selection of BOOT mode.
1.7 Crystal Driver and External Clock Input (XTAL and EXTAL)
These two pins provide the interface for either a crystal or a CMOS compatible clock to control the internal
clock generator circuitry. The frequency applied to these pins is four times higher than the desired E-clock
rate. Refer to Figure 1-5 for crystal and clock connections.
1.8 E-Clock Output (E)
E is the output connection for the internally generated E clock. The signal from E is used as a timing
reference. The frequency of the E-clock output is one fourth that of the input frequency at the XTAL and
EXTAL pins. The E clock can be turned off in single-chip mode for greater noise immunity if desired. See
PC4
PC5
PC6
PC7
XIRQ
PD7
PD6
RESET
IRQ
PD0
PD1
PB2
PB3
PB4
PB5
PB6
PB7
NC
PA0
PA1
PC3
PC2
PC1
PC0
EV
SS
V
SS
XTAL
EXTAL
E
MODA
MODB
PD2
PD3
PD4
PD5
V
DD
PA7
PA6
PA5
PA4
PA3
PA2
2
3
4
5
6
7
8
9
10
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
43
42
41
40
39
38
37
36
35
34
PB1
32
PB0
1
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