參數(shù)資料
型號: MC68HC711A0FB
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: ROM-based high-performance microcontrollers
中文描述: 基于ROM的高性能微控制器
文件頁數(shù): 98/124頁
文件大?。?/td> 840K
代理商: MC68HC711A0FB
TIMING SYSTEM
9-12
TECHNICAL DATA
PR[1:0] — Timer Prescaler Select
These bits are used to select the prescaler divide-by ratio. In normal modes, PR[1:0]
can only be written once, and the write must be within 64 cycles after reset. Refer to
Table 9-1
for specific timing values.
9.3.10 Timer Interrupt Flag 2 Register
Bits in this register indicate when certain timer system events have occurred. Coupled
with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to
operate in either a polled or interrupt driven system. Each bit of TFLG2 corresponds
to a bit in TMSK2 in the same position.
Clear flags by writing a one to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time (Periodic) Interrupt Flag
Refer to
9.4 Real-Time Interrupt
.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to
9.6 Pulse Accumulator
.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to
9.6 Pulse Accumulator
.
Bits [3:0]— Not implemented
Always read zero
9.4 Real-Time Interrupt
The real-time interrupt feature, used to generate hardware interrupts at a fixed periodic
rate, is controlled and configured by two bits (RTR1 and RTR0) in the pulse accumu-
lator control (PACTL) register. The RTII bit in the TMSK2 register enables the interrupt
capability. The four different rates available are a product of the MCU oscillator fre-
quency and the value of bits RTR[1:0]. Refer to the following table, which shows the
periodic real-time interrupt rates.
PR[1:0]
0 0
0 1
1 0
1 1
Prescaler
1
4
8
16
TFLG2
— Timer Interrupt Flag 2
$0025
Bit 7
TOF
0
6
5
4
3
0
0
2
0
0
1
0
0
Bit 0
0
0
RTIF
0
PAOVF
0
PAIF
0
RESET:
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料
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