參數(shù)資料
型號: MC68HC711A0FB
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: ROM-based high-performance microcontrollers
中文描述: 基于ROM的高性能微控制器
文件頁數(shù): 108/124頁
文件大?。?/td> 840K
代理商: MC68HC711A0FB
ELECTRICAL CHARACTERISTICS
A-4
TECHNICAL DATA
NOTES:
1. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four
clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt.
Refer to
SECTION 5 RESETS AND INTERRUPTS
for further detail.
2. All timing is shown with respect to 20% V
DD
and 70% V
DD
, unless otherwise noted.
Figure A-2 Timer Inputs
Table A-4 Control Timing
Characteristic
Symbol
1.0 MHz
Min
dc
1000
dc
300
2.0 MHz
Min
dc
500
dc
175
3.0 MHz
Min
dc
333
dc
133
Unit
Max
1.0
4.0
4.0
Max
2.0
8.0
8.0
Max
3.0
12.0
12.0
Frequency of Operation
E-Clock Period
Crystal Frequency
External Oscillator Frequency
Processor Control SetupTime
t
PCSU
= 1/4 t
cyc
+ 50 ns
Reset Input Pulse Width
To Guarantee External Reset Vector
f
o
MHz
ns
MHz
MHz
ns
t
cyc
f
XTAL
4 f
o
t
PCSU
Minimum Input Time
(Can Be Preempted by Internal Reset)
Mode Programming Setup Time
Mode Programming Hold Time
Interrupt Pulse Width,
IRQ Edge-Sensitive Mode
PW
IRQ
= t
cyc
+ 20 ns
Wait Recovery Startup Time
Timer Pulse Width,
Input Capture Pulse
Accumulator Input
PW
TIM
= t
cyc
+ 20 ns
PW
RSTL
8
1
8
1
8
1
t
cyc
t
cyc
t
MPS
t
MPH
PW
IRQ
2
2
2
t
cyc
ns
ns
10
1020
10
520
10
353
t
WRS
PW
TIM
4
520
4
353
4
t
cyc
ns
1020
NOTES:
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
PA7
2,3
PA7
1,3
PA[2:0]
2
PA[2:0]
1
PW
TIM
TIMER INPUTS TIM
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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