參數(shù)資料
型號(hào): MC68HC711A0FB
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: ROM-based high-performance microcontrollers
中文描述: 基于ROM的高性能微控制器
文件頁數(shù): 75/124頁
文件大?。?/td> 840K
代理商: MC68HC711A0FB
SERIAL COMMUNICATIONS INTERFACE
For More Information On This Product,
Go to: www.freescale.com
TECHNICAL DATA
7-9
The prescale bits, SCP[1:0], determine the highest baud rate and the SCR[2:0] bits se-
lect an additional binary submultiple (
1
, ≥
2,
4
,
through
128) of this highest baud
rate. The result of these two dividers in series is the 16 X receiver baud rate clock. The
SCR[2:0] bits are not affected by reset and can be changed at any time, although they
should not be changed when any SCI transfer is in progress.
Figure 7-3
illustrates the SCI baud rate timing chain. The prescale select bits deter-
mine the highest baud rate. The rate select bits determine additional divide by two
stages to arrive at the receiver timing (RT) clock rate. The baud rate clock is the result
of dividing the RT clock by 16.
Table 7-2 Baud Rate Selects
SCR[2:0]
Divide
Prescaler
By
1
2
4
8
16
32
64
128
Highest Baud Rate
(Prescaler Output from Previous Table)
4800
9600
4800
9600
2400
4800
1200
2400
600
1200
300
600
150
300
150
38.4 K
38.4 K
19.2 K
9600
4800
2400
1200
600
300
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
F
Freescale Semiconductor, Inc.
n
.
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