參數(shù)資料
型號(hào): MC68HC711A0FB
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: ROM-based high-performance microcontrollers
中文描述: 基于ROM的高性能微控制器
文件頁數(shù): 84/124頁
文件大?。?/td> 840K
代理商: MC68HC711A0FB
SERIAL PERIPHERAL INTERFACE
8-6
TECHNICAL DATA
8.5.1 Serial Peripheral Control
SPIE — Serial Peripheral Interrupt Enable
0 = SPI interrupt disabled
1 = SPI interrupt enabled
SPE — Serial Peripheral System Enable
0 = SPI off
1 = SPI on
DWOM — Port D Wired-OR Mode
DWOM affects all six port D pins.
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR — Master Mode Select
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of
the master device has a steady state low value. When CPOL is set, SCK idles high.
Refer to
Figure 8-2
and
8.2.1 Clock Phase and Polarity Controls
.
CPHA — Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relation-
ship between master and slave. The CPHA bit selects one of two different clocking
protocols. Refer to
Figure 8-2
and
8.2.1 Clock Phase and Polarity Controls
.
SPR1 and SPR0 — SPI Clock Rate Selects
These two serial peripheral rate bits select one of four baud rates to be used as SCK
if the device is a master; however, they have no effect in the slave mode.
SPCR
— Serial Peripheral Control Register
$0028
Bit 7
SPIE
0
6
5
4
3
2
1
Bit 0
SPR0
U
SPE
0
DWOM
0
MSTR
0
CPOL
0
CPHA
1
SPR1
U
RESET:
SPR[1:0]
0 0
0 1
1 0
1 1
E Clock
Divide By
2
4
16
32
Frequency at
E = 2 MHz (Baud)
1.0 MHz
500 kHz
125 kHz
62.5 kHz
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料
PDF描述
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