參數(shù)資料
型號： MC68HC705L16CFU
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁數(shù)： 117/146頁
文件大?。?/td> 852K
代理商： MC68HC705L16CFU
Simple Serial Peripheral Interface (SSPI)
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
72
Freescale Semiconductor
Figure 8-3. SSPI Clock-Data Timing Diagram
8.5.2 Serial Clock (SCK)
SCK is used for synchronization of both input and output data streams through its SDI and SDO pins.
The master and slave devices are capable of exchanging a data byte during a sequence of eight clock
pulses. Since the SCK is generated by the master, slave data transfer is accomplished by synchronization
to SCK.
The master generates the SCK through a circuit driven by the internal processor clock and uses the SCK
to latch incoming slave device data on the SDI pin and shift out data to the slave via the SDO pin. The
SPR bit in the SPCR of the master selects the transmission clock rate.
The slave device receives the SCK from the master device, and uses the SCK to latch incoming master
device data on the SDI pin and shifts out data to the master via the SDO pin. The SPR bit in the SPCR of
the slave has no meaning.
NOTE
PC2/SCK should be at VDD level before SSPI is enabled. This can be done
with an internal or external pullup resistor or by setting DDRC2 = 1 and PC2
= 1 prior to enabling the SSPI. Otherwise, the circuit will not initialize
correctly.
MSB
BIT6
BIT5
BIT3
BIT2
BIT1
LSB
BIT4
SCK
SDO
DORD = 0
MSB
BIT6
BIT5
BIT3
BIT2
BIT1
LSB
BIT4
SDI
DORD = 0
LSB
BIT1
BIT2
BIT4
BIT5
BIT6
MSB
BIT3
SDO
DORD = 1
LSB
BIT1
BIT2
BIT4
BIT5
BIT6
BIT3
SDI
DORD = 1
DATA
SAMPLE
MSB
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