參數(shù)資料
型號： MC68HC705L16CFU
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁數(shù)： 108/146頁
文件大?。?/td> 852K
代理商： MC68HC705L16CFU
Oscillators/Clock Distributions
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
64
Freescale Semiconductor
7.5.4 COP
The computer operating properly (COP) watchdog timer is controlled by the COPE and COPC bits in the
TBCR2 register.
The COP uses the same clock as TBI that is selected by the TBR1 and TBR0 bits. The TBI is divided by
four and overflow of this divider generates COP timeout reset if the COP enable (COPE) bit is set. The
COP timeout reset has the same vector address as POR and external RESET. To prevent the COP
timeout, the COP divider is cleared by writing a logic1 to the COP clear (COPC) bit.
When the timebase divider is driven by the OSC clock, clock for the divider is suspended during stop
mode or when FOSCE is a logic 0. This may cause COP period stretching or no COP timeout reset when
processing errors occur. To avoid these problems, it is recommended that the XOSC clock be used for
the COP functions.
When the timebase (COP) divider is driven by the XOSC clock, the divider does not stop counting and
the COPC bit must be triggered to prevent the COP timeout.
Table 7-3. Timebase Interrupt Frequency
TBCR2
Divide Ratio
Frequency (Hz)
TBR
1
TBR
0
OSC = 4.0 M
OSC = 4.1943 M
XOSC = 32.768 k
00
TBCLK
÷ 128
244
256
01
TBCLK
÷ 4096
7.63
8.00
10
TBCLK
÷ 8192
3.81
4.00
11
TBCLK
÷ 16,384
1.91
2.00
Table 7-4. COP Timeout Period
TBCR2
COP Period (ms)
TBR1
TBR0
OSC = 4.0 MHz
OSC = 4.1943 MHz
XOSC = 32.768 kHz
Min
Max
Min
Max
Min
Max
0
12.3
16.4
11.7
15.6
11.7
15.6
0
1
393
524
375
500
375
500
1
0
786
1048
750
1000
750
1000
1
1573
2097
1500
2000
1500
2000
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