參數(shù)資料
型號： MC68HC705L16CFU
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁數(shù)： 107/146頁
文件大小： 852K
代理商： MC68HC705L16CFU
Timebase
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
63
7.5 Timebase
Timebase is a 14-bit up-counter which is clocked by XOSC input or OSC input divided by 128. TBCLK bit
in the TBCR1 register selects the clock source.
This 14-bit divider is initialized to $0078 only upon power-on reset (POR). After counting 8072 clocks, the
STUP bit in the MISC register is set.
The divided clocks from the timebase are used for LCDCLK, STUP, TBI, and COP. (See Figure 7-4).
7.5.1 LCDCLK
The clocks divided by 64 and 128 are used as LCD clocks at the LCD driver module, and clocks are
selected by the LCLK bit in the TBCR1.
Figure 7-4. Timebase Clock Divider
7.5.2 STUP
Timebase divider is initialized to $0078 by the power-on detection. When the count reaches 8072, the
STUP flag in the MISC register is set. Once the STUP flag is set, it is never cleared until power down.
7.5.3 TBI
Timebase interrupts may be generated every 0.5, 0.25, 0.125, or 0.0039 seconds with a 32.768-kHz
crystal at XOSC pins.
The timebase interrupt flag (TBIF) is set every period and interrupt is requested if the enable bit (TBIE) is
set. The clock divided by 128, 4096, 8192, or 16,384 is used to set TBIF, and this clock is selected by the
TBR1 and TBR0 bits in the TBCR2 register. (See Table 7-3.)
SEL
7-BIT
DIVIDER
SEL
DIVIDE BY 4
TBIF
TBCLK
LCLK
TBIE
7-BIT
DIVIDER
TBR1
TBR0
COP ENABLE
COP CLEAR
COP
RESET
TBI
LCD
CLOCK
1/26
1/27
1/20
1/25
1/26
1/27
XCLK
OSC/27
0
1
0
1
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