參數(shù)資料
型號： MC68HC705E6
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： HCMOS Microcontroller Unit
中文描述： HCMOS微控制器
文件頁數(shù)： 76/140頁
文件大?。?/td> 788K
代理商： MC68HC705E6
Resets and Interrupts
MC68HC05E6 — Rev. 1.0
Resets and Interrupts
providing the corresponding enable bit stored on the stack is zero, i.e.
the interrupt is disabled.
Unlike reset, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete. The current instruction is the one already fetched
and being operated on. When the current instruction is complete, the
processor checks all pending hardware interrupts. If interrupts are not
masked (CCR I-bit clear) and the corresponding interrupt enable bit is
set, the processor proceeds with interrupt processing; otherwise, the
next instruction is fetched and executed.
NOTE:
Power-on or external reset clear all interrupt enable bits thus preventing
interrupts during the reset sequence.
Interrupt priorities
Each potential interrupt source is assigned a priority which means that if
more than one interrupt is pending at the same time, the processor will
service the one with the highest priority first. For example, if both an
external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced first.
Table 11
shows the relative priorities of all the possible interrupt
sources.
Figure 19
shows the interrupt processing flow.
Table 11 Interrupt priorities
Source
Reset
Register
—
—
—
CTCSR
LVIOPT
TSR
KEY/TIM
Flags
—
—
—
Vector address
$1FFE, $1FFF
$1FFC, $1FFD
$1FFA, $1FFB
$1FF8, $1FF9
$1FF6–$1FF7
$1FF4, $1FF5
$1FF2, $1FF3
Priority
highest
Software interrupt (SWI)
External interrupt (IRQ)
Core timer
Low voltage interrupt
16-bit timer
Keyboard interrupt
CTOF, RTIF
LVIINT
ICF, OCF, TOF
KSF
4-resets
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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相關代理商/技術參數(shù)
參數(shù)描述
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