參數(shù)資料
型號： MC68HC705CJ4FB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44
封裝： PLASTIC, QFP-44
文件頁數(shù)： 59/114頁
文件大?。?/td> 4047K
代理商： MC68HC705CJ4FB
GENERAL RELEASE SPECIFICATION
SERIAL COMMUNICATIONS INTERFACE
MC68HC(7)05CJ4
8-12
Rev. 2.1
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8.3.3 Idle Line Detect
The receive logic hardware includes the ability to detect an idle line. This can be
useful in a system to indicate when one message was finished and another was
about to be started. An idle line is defined as a minimum of 10 (11 if nine data bit
format is selected) bit times of continuous logic ones on the RXD line. During a
normal message, there is no idle time between frames, so even if all information
bits in a frame were logic ones the start bits would ensure that at least one logic
zero bit time occurred for each frame and IDLE would not get set.
When the RXD line goes idle for the minimum required time, the IDLE status bit in
SCSR gets set. If the Idle Line Interrupt Enable (ILIE) bit in the SCCR1 register is
set then a hardware interrupt sequence also will be requested when IDLE gets set.
The IDLE status bit is cleared by reading the SCSR register (with IDLE set)
followed by reading the RDR register. IDLE will not be set again until after at least
one character is received. This prevents an RXD line that remains idle for a long
period of time from causing several interrupts.
8.3.4 Receiver Wakeup
The receiver logic hardware also supports a receiver wake-up function intended for
systems having more than one receiver. With this function, the transmitting device
directs messages to an individual receiver or group of receivers by passing
addressing information as the initial byte(s) of each message. Receivers not
addressed invoke the receiver wake up function which puts these receivers in a
dormant state for the remainder of the unwanted message. This eliminates any
further software overhead to service the remaining characters of the unwanted
message and thus improves performance.
The receiver is placed in wake-up mode by writing a one to the receiver wake-up
(RWU) bit in the SCCR2 register. While RWU is set, all of the receive status flags
(RDRF, IDLE, OR, NF, and FE) are inhibited (cannot be set). Note that
specification of receiver wake-up mode inhibits the use of the idle line detect
function. Although RWU may be cleared by a write to SCCR, it is normally left alone
by software and gets cleared automatically by hardware with one of the two
methods explained in the following paragraphs.
The SCI offers a choice of two methods for waking up receivers from the dormant
state. The first method is called idle line wake up. The second method is called
address mark wake up and operates by using the MSB to differentiate between
address information (MSB set) and data information (MSB clear). The WAKE
control bit in the SCCR1 control register is used to select which method of
automatic hardware wake up is to be used. If the WAKE bit is clear, Idle Line wake
up is specified and if WAKE is set to one, address mark wake up is selected.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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