參數(shù)資料
型號: MC68HC705CJ4FB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 51/114頁
文件大?。?/td> 4047K
代理商: MC68HC705CJ4FB
GENERAL RELEASE SPECIFICATION
SERIAL COMMUNICATIONS INTERFACE
MC68HC(7)05CJ4
8-4
Rev. 2.1
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A few definitions will help in understanding the following discussions.
Bit Time
A bit time is the period of time required to serially transmit or receive one bit of
data and is equal to one cycle of the baud rate frequency.
Mark/Space
Standard NRZ format is sometimes called mark/space format where a mark is
a bit time of logic one and a space is a bit time of logic zero.
Start Bit
A start bit is a bit time of logic zero which indicates the beginning of a data frame.
A start bit must begin with a one to zero transition and is preceded by at least
one bit time of logic one.
Stop Bit
A stop bit is one bit time of logic one which indicates the end of a data frame.
Frame
A frame consists of a start bit followed by a specified number of data or
information bits terminated by a stop bit. The number of data or information bits
depends on the format specified and must agree between the transmitting
device and the receiving device. The most common frame format is one start bit
followed by eight data bits (LSB first) terminated by one stop bit for a total of ten
bit times in the frame. This device is also capable of operating in a nine data bit
format as described elsewhere in this specification.
When the receiver is first enabled, by writing a one to the RE bit in the SCCR2
register, the receiver front end logic begins an asynchronous search for a start bit.
The goal of this search is to gain synchronization with a frame. This bit time
synchronization is done at the beginning of each frame so that small differences in
the baud rate of the receiver and transmitter are not cumulative. The circuit also
resynchronizes on all one-to-zero transitions in the serial data stream.
The sequence of events in searching for a start bit is as follows:
1. Sample RXD input during each RT period and maintain these samples in a
serial pipeline.
* if RXD is already low, do not begin the start bit search - go to step 1.
* if RXD is high, look for two more high RT samples before beginning the
start bit search. Stay in step 1 until a total of three consecutive high RT
samples have been received.
2. RXD was low during this RT period and high during the previous three
periods. Consider this sample to be time “RT1 and the official start of the
start bit search.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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