參數(shù)資料
型號： MC68HC705C9AP
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 139/177頁
文件大?。?/td> 1941K
代理商： MC68HC705C9AP
Resets
Advance Information
MC68HC705C9A — Rev. 4.0
64
Resets
MOTOROLA
5.8 MC68HC05C12A Compatible COP Clear Register
The COP clear register, shown in Figure 5-6, resets the C12A COP
counter.
COPC — Computer Operating Properly Clear Bit
Preventing a COP reset is achieved by writing a 0 to the COPC bit.
This action will reset the counter and begin the timeout period again.
The COPC bit is bit 0 of address $3FF0. A read of address $3FF0 will
result in the data programmed into the mask option register PBMOR.
5.9 COP During Wait Mode
Either COP will continue to operate normally during wait mode. The
software must pull the device out of wait mode periodically and reset the
COP to prevent a system reset.
5.10 COP During Stop Mode
Stop mode disables the oscillator circuit and thereby turns the clock off
for the entire device. The COP counter will be reset when stop mode is
entered. If a reset is used to exit stop mode, the COP counter will be
reset after the 4064 cycles of delay after stop mode. If an IRQ is used to
exit stop mode, the COP counter will not be reset after the 4064-cycle
delay and will have that many cycles already counted when control is
returned to the program.
$3FF0
Bit 7
6543
2
1
Bit 0
Read:
Write:
COPC
Reset:
000
U
0
= Unimplemented
U = Undetermined
Figure 5-6. COP Clear Register (COPCLR)
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