參數(shù)資料
型號(hào): MC68HC705C9ACS
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER
文件頁數(shù): 48/177頁
文件大?。?/td> 1941K
代理商: MC68HC705C9ACS
Electrical Specifications
3.3-Vdc Control Timing
MC68HC705C9A — Rev. 4.0
Advance Information
MOTOROLA
Electrical Specifications
141
Figure 12-7. Power-On Reset Timing Diagram
Figure 12-8. External Reset Timing
3FFE
4064 t
CYC
V
DD
OSC1 PIN
(2)
INTERNAL
CLOCK(3)
INTERNAL
DATA BUS
(3)
3FFE
3FFF
(NOTE 1)
1. Power-on reset threshold is typically between 1 V and 2 V.
3. Internal clock, internal address bus, and internal data bus are not available externally.
NEW
PCH
NEW
PCL
2. OSC1 line is meant to represent time only, not frequency.
4. RESET outputs VOL during 4064 POR cycles.
Notes:
RESET PIN
(NOTE 4)
INTERNAL
ADDRESS BUS(3)
INTERNAL
CLOCK(1)
INTERNAL
ADDRESS BUS(1)
Notes:
INTERNAL
DATA BUS(1)
3FFE
3FFF
NEW PC
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
NEW
PCH
t
RL
NEW
PCL
OP
CODE
RESET
(2)
3FFE
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