參數資料
型號: MC68HC705C9ACS
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER
文件頁數: 126/177頁
文件大?。?/td> 1941K
代理商: MC68HC705C9ACS
Interrupts
Advance Information
MC68HC705C9A — Rev. 4.0
52
Interrupts
MOTOROLA
NOTE:
The current instruction is the one already fetched and being operated on.
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and if the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If an external interrupt and a timer, SCI, or SPI interrupt are pending at
the end of an instruction execution, the external interrupt is serviced first.
The SWI is executed the same as any other instruction, regardless of the
I-bit state.
Table 4-1 shows the relative priority of all the possible interrupt sources.
Figure 4-1 shows the interrupt processing flow.
Table 4-1. Vector Addresses for Interrupts and Resets
Function
Source
Local
Mask
Global
Mask
Priority
(1 = Highest)
Vector
Address
Reset
Power-on reset
None
1
$3FFE–$3FFF
RESET pin
COP watchdog
Software
interrupt
(SWI)
User code
None
Same priority
as instruction
$3FFC–$3FFD
External
interrupt
IRQ pin port B pins
None
I bit
2
$3FFA–$3FFB
Timer
interrupts
ICF bit
ICIE bit
I bit
3
$3FF8–$3FF9
OCF bit
OCIE bit
TOF bit
TOIE bit
SCI
interrupts
TDRE bit
TCIE bit
I bit
4
$3FF6–$3FF7
TC bit
RDRF bit
RIE bit
OR bit
IDLE bit
ILIE bit
SPI
interrupts
SPIF bit
SPIE
I bit
5
$3FF4–$3FF5
MODF bit
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