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參數(shù)資料
| 型號： | MC68HC68T1 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Real-Time Clock plus RAM with Serial Interface |
| 中文描述： | 實時時鐘加RAM的串行接口 |
| 文件頁數(shù)： | 20/26頁 |
| 文件大?。?/td> | 342K |
| 代理商： | MC68HC68T1 |
MC68HC68T1
20
MOTOROLA
BRIDGE/
REGULATOR
AC LINE
MC68HC68T1
MC68HC05C4
VDD
VDD
POR
VBATT
LINE
CPUR
RESET
VSYS
INT
IRQ
CLKOUT
SS
MISO
MOSI
SCK
OSC 1
PORT (e.g., PC0)
MISO
MOSI
SCK
NOTE 2
NOTE 1
NOTE 3
VDD
100 k
0.1 F
13
16
10
40
14
15
11
12
3
2
7
6
5
4
2
1
28
31
32
33
39
1
RCHARGE
NOTES:
1. The LINE input pin can sense when the switch opens by use of the power sense interrupt. The MC68HC68T1 crystal
drives the clock input to the CPU using the CLKOUT pin. On power–down when VSYS < VBATT + 0.7 V, VBATT
powers the clock. A threshold detect activates an on–chip P channel switch, connecting VBATT to VDD. VBATT
always supplies power to the oscillator, keeping voltage frequency variation to a minimum.
2. For 32.768 kHz oscillator, see Figure 12. This configuration, when the MC68HC68T1 supplies the MCU clock, usually
requires a 1 to 4 MHz clock.
3. If an MC68HC11 MCU is used, delete the capacitor at the RESET pin.
Figure 19. Externally–Controlled Power System
POWER–SENSING POWER–DOWN PROCEDURE
A procedure for power–down operation consists of the fol-
lowing:
1. Set power sense operation by writing bit 5 high in the
interrupt control register.
2. When an interrupt occurs, the CPU reads the status
register to determine the interrupt source.
3. Sensing a power failure, the CPU does the necessary
housekeeping to prepare for shutdown.
4. The CPU reads the status register again after several
milliseconds to determine validity of power failure.
5. The CPU sets power–down (bit 6) and disables all
interrupts in the interrupt control register when
power–down is verified. This causes the CPU reset and
Clock Out pins to be held low and disconnects the serial
interface.
6. When power returns and VSYS rises above VBATT +
0.7 V, power–up is initiated. The CPU reset is released
and serial communication is established.
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