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參數(shù)資料
| 型號： | MC68HC58DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 74/102頁 |
| 文件大小： | 700K |
| 代理商： | MC68HC58DW |
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MC68HC58
CONTROL AND STATUS CODES
MOTOROLA
TECHNICAL DATA
5-7
If the command is latched while a frame is being received, all bytes in the RxFIFO buff-
er and all subsequent bytes received before the completion code is generated, are
flushed.
In the two previous instances, the RxFIFO status (RFS) field in the status byte may be
invalid until the completion code is recognized.
If the command is latched while the first byte in the RxFIFO buffer is a completion
code, the RxFIFO buffer is not flushed.
5.2 Configuration Byte
The fields in the configuration byte determine the basic operational parameters of the
DLC.
A host MCU cannot read configuration information from the DLC. Once a configuration
byte is sent to the DLC, operating parameters cannot change until a new byte is sent,
or a reset occurs.
5.2.1 TM — Test Mode Control Bit
Setting the TM bit enables the receive data disable test mode. This mode is used for
Motorola internal testing only.
0 = Normal operation
1 = Test mode
5.2.2 TC[6:5] — Test Configuration Field
The TC bit field selects one of four operating modes. When TC value is %00 (default),
the DLC operates normally. Each of the other values selects a test mode. These
modes are used for Motorola internal testing only.
5.2.3 IMSK — Interrupt Mask Bit
The IMSK bit determines DLC interrupt request capability. When interrupts are dis-
abled, the DLC cannot exit standby mode upon detection of J1850 bus activity.
0 = All interrupts to the MCU are enabled
1 = All interrupts to the MCU are disabled
CBR — Configuration Byte Register
7
6
5
4
3
2
1
0
TM
TC
IMSK
IMOD
OSCD
4X
RESET:
0
1
0
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