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參數(shù)資料
| 型號： | MC68HC58DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 39/102頁 |
| 文件大?。?/td> | 700K |
| 代理商： | MC68HC58DW |
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MC68HC58
J1850 FRAME FORMAT
MOTOROLA
TECHNICAL DATA
3-7
3.2.1 Invalid Passive Bit
If the passive to active transition beginning the next data bit or symbol occurs between
A (the active to passive transition beginning the current data bit or symbol) and B, the
current bit is invalid. Refer to Figure 3-4 (1).
3.2.2 Valid Passive Logic Zero
If the passive to active transition beginning the next data bit or symbol occurs between
B and C, the current bit is considered a logic zero. Refer to Figure 3-4 (2).
3.2.3 Valid Passive Logic One
If the passive to active transition beginning the next data bit or symbol occurs between
C and D, the current bit is considered a logic one. Refer to Figure 3-4 (3).
3.2.4 Valid EOD Symbol
If the passive to active transition beginning the next data bit or symbol occurs between
D and E, the current symbol is considered a valid EOD symbol. Refer to Figure 3-4 (4).
3.2.5 Valid EOF and IFS Symbol
If the passive to active transition beginning the SOF symbol of the next frame occurs
between E and F, the current symbol is considered a valid EOF symbol. If the passive
to active transition beginning the SOF symbol of the next frame occurs between F and
G, the current symbol is considered a valid EOF symbol, followed by a valid IFS sym-
bol. All nodes must wait until a valid IFS symbol time has expired before beginning
transmission. However, due to variations in clock frequencies and J1850 bus loading,
some nodes may recognize a valid IFS symbol before others, and immediately begin
transmitting. Therefore, any time a node waiting to transmit detects a passive to active
transition once a valid EOF has been detected, it should immediately begin transmis-
sion, initiating the arbitration process. Refer to Figure 3-4 (5 and 6).
3.2.6 Idle Bus
If the passive to active transition beginning the SOF symbol of the next frame does not
occur before G, the J1850 bus is considered to be idle, and any node wishing to trans-
mit a frame may do so immediately. Refer to Figure 3-4 (6).
3.2.7 Invalid Active Bit
If the active to passive transition beginning the next data bit or symbol occurs between
A (the passive to active transition beginning the current data bit or symbol) and B, the
current bit is invalid. Refer to Figure 3-5 (1).
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