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參數(shù)資料
| 型號： | MC68HC58DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 41/102頁 |
| 文件大?。?/td> | 700K |
| 代理商： | MC68HC58DW |
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MC68HC58
J1850 FRAME FORMAT
MOTOROLA
TECHNICAL DATA
3-9
3.2.10 Valid SOF Symbol
If the active to passive transition beginning the next data bit or symbol occurs between
D and E, the current symbol is considered a valid SOF symbol. Refer to Figure 3-5 (4).
3.2.11 Valid BREAK Symbol
If the next active to passive transition does not occur between E and F, the current
symbol is considered a valid BREAK symbol. Following the BREAK symbol, an IFS
period must be observed, after which normal communication can resume on the J1850
bus. Refer to Figure 3-5 (5).
3.3 Frame Arbitration
Frame arbitration on the J1850 bus is accomplished in a non-destructive manner, al-
lowing the frame with the highest priority to be transmitted. Transmitters which lose ar-
bitration simply stop transmitting and wait for an idle J1850 bus to begin transmitting
again.
If the DLC wishes to transmit onto the J1850 bus, but detects that another frame is in
progress, it must wait until the J1850 bus is idle. However, if multiple nodes begin to
transmit in the same synchronization window, frame arbitration occurs beginning with
the first bit after the SOF symbol, and continues with each bit thereafter.
The VPW symbols and J1850 bus electrical characteristics are carefully chosen so
that a logic zero (active or passive type) always dominates over a logic one (active or
passive type) simultaneously transmitted. Hence logic zeros are said to be “dominant”
and logic ones are said to be “recessive”. Whenever a node detects a dominant bit
when it transmitted a recessive bit, it loses arbitration, and immediately stops transmit-
ting. This is known as “bitwise arbitration”. Refer to Figure 3-6.
Figure 3-6 J1850 VPW Bitwise Arbitration
TRANSMITTER A
TRANSMITTER B
J1850 BUS
SOF
DATA
BIT 1
DATA
BIT 4
DATA
BIT 5
“0”
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS, AND STOPS
TRANSMITTING
TRANSMITTER B WINS
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
“0”
“1”
DATA
BIT 2
“1”
DATA
BIT 3
“0”
“1”
ARBITRATION AND
CONTINUES
TRANSMITTING
J1850 BIT ARB
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