參數(shù)資料
型號(hào)： MC68HC2681P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 34/88頁(yè)
文件大?。?/td> 461K
代理商： MC68HC2681P
MOTOROLA
MC68HC681 USER’S MANUAL
v
TABLE OF CONTENTS
Paragraph
Page
Number
Title
Number
Section 1
Introduction
1.1
Internal Control Logic ........................................................................... 1-4
1.2
Timing Logic ......................................................................................... 1-4
1.3
Interrupt Control Logic.......................................................................... 1-5
1.4
Data Bus Buffer .................................................................................... 1-5
1.5
Communication Channels A and B ...................................................... 1-5
1.6
Input Port.............................................................................................. 1-5
1.7
Output Port ........................................................................................... 1-6
Section 2
Signal Descriptions
2.1
VCC and GND ....................................................................................... 2-2
2.2
Crystal Input or External CLOCK (X1).................................................. 2-2
2.3
Crystal Input (X2) ................................................................................. 2-3
2.4
RESET (RESET) .................................................................................. 2-3
2.5
Chip-Select (CS) .................................................................................. 2-3
2.6
Read/Write (R/W) ................................................................................. 2-3
2.7
Data Transfer Ackowledge (DTACK) ................................................... 2-4
2.8
Register-Select Bus (RS1–RS4) .......................................................... 2-4
2.9
Data Bus (D0–D7) ................................................................................ 2-4
2.10
Interupt Request (IRQ) ......................................................................... 2-4
2.11
Interupt Ackowledge (IACK) ................................................................. 2-4
2.12
Channel A/B Transmitter Serial-Data Output (TxDA/TxDB)................. 2-4
2.13
Channel A/B Receiver Serial-Data Input (RxDA/RxDB)....................... 2-4
2.14
Parallel Inputs (IP0–IP5) ...................................................................... 2-4
2.14.1
IP0 .............................................................................................. 2-4
2.14.2
IP1 .............................................................................................. 2-5
2.14.3
IP2 .............................................................................................. 2-5
2.14.4
IP3 .............................................................................................. 2-5
2.14.5
IP4 .............................................................................................. 2-5
2.14.6
IP5 .............................................................................................. 2-5
2.15
Parallel Outputs (OP0–OP7) ................................................................ 2-5
2.15.1
OP0 ............................................................................................ 2-5
2.15.2
OP1 ............................................................................................ 2-5
2.15.3
OP2 ............................................................................................ 2-6
2.15.4
OP3 ............................................................................................ 2-6
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