參數(shù)資料
型號： MC68HC2681P
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 24/88頁
文件大?。?/td> 726K
代理商： MC68HC2681P
Operation
MOTOROLA
MC68HC681 USER’S MANUAL
3-7
3
Customers can program the counter to generate an interrupt request for this condition on
the IRQ output or output pin OP3. After 000016 the counter counts to FFFF16, and continues
counting down from there. If the CPU changes the preload value, the counter will not
recognize the new value until it receives the next start counter command (and is
reinitialized). When a read at the stop counter command address is performed, the counter
stops the countdown sequence and clears ISR[3]. The count value should only be read while
the counter is stopped because only one of the count registers (either CUR or CLR) can be
read at a time. If the counter is running, a decrement of CLR that requires a borrow from the
CUR could take place between the two reads.
3.5.2 Timer Mode
In timer mode, the C/T generates a square-wave output derived from the programmed timer
input (clock source). The timer clock source can be the external clock on the X1 input pin
divided by one or sixteen, or it can be an external input on input port pin IP2 divided by one
or sixteen. The square wave generated by the timer has a period of 2x (preload value) x
(period of clock source), is available as a clock source for both communications channels
and can be programmed to appear on output pin OP3. The timer runs continuously; the CPU
cannot stop it. Because the timer cannot be stopped, the count value (CUR:CLR) should not
be read. When a read at the start counter command address is performed, the timer
terminates the current countdown sequence, sets its output to 1 (appears uninverted at
OP3), is initialized to the preload value, and begins a new countdown sequence. When the
counter counts from 000116 (terminal count), it inverts its output, is re-initialized to the
preload value and repeats the countdown sequence. After reaching terminal count a second
time, the timer sets the C/T-ready bit in the interrupt status register (ISR[3]), inverts its
output, is re-initialized again, and begins a new countdown sequence. Customers can
program the timer to generate an interrupt request for this condition (every second
countdown cycle) on the IRQ output. If the CPU changes the preload value, the timer will
not recognize the new value until either (a) it reaches the next terminal count and is
reinitialized automatically, or (b) it is forced to re-initialize by a start command. When a read
at the stop counter command address is performed, the timer clears ISR[3] but does not
stop. Because in timer mode the C/T runs continuously, it should be completely configured
(preload value loaded and start counter command issued) before programming the timer
output to appear on OP3.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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