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| 型號： | MC68HC2681P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 19/88頁 |
| 文件大?。?/td> | 726K |
| 代理商： | MC68HC2681P |
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Operation
MOTOROLA
MC68HC681 USER’S MANUAL
3-3
3
The receiver can detect a break that starts in the middle of a character provided the break
persists completely through the next character time or longer. When the break begins in the
middle of a character, the receiver will place the damaged character in a holding register
with the framing error bit set. Then, provided the break persists through the next character
time, the receiver will also place an all-zero character in the next holding register with the
received-break bit set.
The parity error, framing error, overrun error, and received-break conditions (if any) set error
and break flags in the status register at the received character boundary and are valid only
when the receiver-ready bit (RxRDY) in the status register is set. A first-in first-out (FIFO)
stack is used in each channel’s receive buffer logic and consists of three receive holding
registers. The receiver buffer (RBA or RBB) is composed of the FIFO and a receive shift
register connected to the receiver serial-data input. Data is assembled in the shift register
and loaded into the top-most empty FIFO receive holding register position. Thus, data
flowing from the receiver to the CPU is quadruply buffered.
The receiver-ready bit in the status register (SRA or SRB) is set whenever one or more
characters are available to be read. A read of the receiver buffer produces an output of data
from the top of the FIFO stack. After the read cycle, the data at the top of the FIFO stack and
its associated status bits are "popped" and new data can be added at the bottom of the stack
by the receive shift register. The FIFO-full status bit is set if all three stack positions are filled
with data. Either the receiver-ready or the FIFO-full status bits can be selected to cause an
interrupt. In addition to the data byte, three status bits (parity error, framing error, and
received break) are appended to each data character in the FIFO (overrun is not). By
programming the error-mode control bit in the channel’s mode register, status can be
provided for "character" or "block" modes.
In the "character" mode, the status register (SRA or SRB) is updated on a character-by-
character basis and applies only to the character at the top of the FIFO. Thus, the status
must be read before the character is read. Reading the character pops it and its error flags
off the FIFO.
In the "block" mode, the status provided in the status register for the parity error, framing
error, and received-break conditions is the logical OR of these respective bits for all
characters coming to the top of the FIFO stack since the last reset error command was
issued. That is, beginning at the last reset-error command issued, a continuous logical-OR
function of corresponding status bits is produced in the status register as each character
comes to the top of the FIFO stack.
The block mode is useful in applications requiring the exchange of blocks of information
where the software overhead of checking each character’s error flags cannot be tolerated.
In this mode, entire messages can be received and only one data integrity check is
performed at the end of each message. Although data reception in this manner has speed
advantages, there are also disadvantages. Because each character is not individually
checked for error conditions by the software, if an error occurs within a message the error
will not be recognized until the final check is performed. Also, there is no indication of which
character(s) is in error within the message.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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