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| 型號： | MC68HC2681P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 20/88頁 |
| 文件大小： | 726K |
| 代理商： | MC68HC2681P |
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Operation
3-4
MC68HC681 USER’S MANUAL
MOTOROLA
3
The block mode can only be used if either (or both) of two conditions can be guaranteed:
1. The length of the block is known before the last character of the block is read, so that
the block error status can be read and cleared before reading the last character;
2. There will never be another character already present in the FIFO until the last char-
acter of the message is read (leaving the FIFO empty), the status is read, and a reset
error command is issued. Otherwise, errors in the first character of the next block could
be reported erroneously on the current block, or they could be prematurely cleared and
not reported in the error status of the next block.
In either mode, reading the status register (SR) does not affect the FIFO. The FIFO is
"popped" only when the receive buffer (RBA or RBB) is read. If all three of the FIFO’s receive
holding registers are full when a new character is received, that character is held in the
receive shift register until a FIFO position is available. If an additional character is received
while this state exists, the contents of the FIFO are not affected, but the character previously
in the shift register is lost and the overrun-error status bit will be set upon receipt of the start
bit of the new overrunning character.
To support flow control, a receiver can automatically negate and reassert the ready-to-
receive (RTR) output (alternate function of parallel outputs OP0 and OP1). The RTS and
RTR functions both use OP0 (channel A) and/or OP1 (channel B). Both functions should not
be enabled for the same channel at the same time. If programmed to operate in this mode,
the ready-to-receive output will automatically be negated by the receiver when a valid start
bit is received and the FIFO stack is full. When a FIFO position becomes available, the
ready-to-receive output will be reasserted automatically by the receiver. Connecting the
ready-to-receive output to the clear-to-send (CTS) input of a transmitting device, prevents
overrun errors in the receiver. The RTR output must be manually asserted the first time.
Thereafter, the receiver will control the RTR output.
If the FIFO stack contains characters and the receiver is then disabled, the characters in the
stack can still be read but no additional characters can be received until the receiver is again
enabled. If the receiver is disabled while receiving a character, or while there is a character
in the shift register waiting for a FIFO opening, these characters are lost. If the receiver is
reset, the FIFO stack and all of the receiver status bits, the corresponding output ports, and
the interrupt request are reset. No additional characters can be received until the receiver is
again enabled.
3.3 LOOPING MODES
Besides the normal operation mode in which the receiver and transmitter operate
independently, each DUART channel can be configured to operate in various looping modes
that are useful for local and remote system diagnostic functions. These modes are described
in the following paragraphs with additional information available in Section 4 Programming
and Register Descriptions.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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