Advance Information
MC68HC912B32 MC68HC12BE32 — Rev. 3.0
18
List of Figures
MOTOROLA
List of Figures
Figure
Title
Page
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . . .113
Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . .114
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . . .115
Port B Data Direction Register (DDRB) . . . . . . . . . . . . . . . . .116
Port E Data Register (PORTE). . . . . . . . . . . . . . . . . . . . . . . .117
Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . .118
Port E Assignment Register (PEAR) . . . . . . . . . . . . . . . . . . .119
Pullup Control Register (PUCR). . . . . . . . . . . . . . . . . . . . . . .122
Reduced Drive of I/O Lines (RDRIV) . . . . . . . . . . . . . . . . . . .123
7-1
7-2
7-3
7-4
7-5
EEPROM Block Protect Mapping. . . . . . . . . . . . . . . . . . . . . .127
EEPROM Module Configuration Register (EEMCR) . . . . . . .128
EEPROM Block Protect Register (EEPROT) . . . . . . . . . . . . .129
EEPROM Test Register (EETST). . . . . . . . . . . . . . . . . . . . . .130
EEPROM Control Register (EEPROG) . . . . . . . . . . . . . . . . .131
8-1
8-2
8-3
8-4
8-5
8-6
FLASH EEPROM Lock Control Register (FEELCK). . . . . . . .137
FLASH EEPROM Module Configuration Register (FEEMCR)138
FLASH EEPROM Module Test Register (FEETST). . . . . . . .138
FLASH EEPROM Control Register (FEECTL) . . . . . . . . . . . .140
Program Sequence Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Erase Sequence Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10 Clock Chain for SCI, BDLC, RTI, and COP . . . . . . . . . . . . . .167
10-11 Clock Chain for TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
10-12 Clock Chain for ECT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
10-13 Clock Chain for SPI, ATD, and BDM . . . . . . . . . . . . . . . . . . .170
CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
CGM Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Internal Clock Relationships in Normal Run Modes . . . . . . . .158
Internal Clock Relationships in Wait Mode. . . . . . . . . . . . . . .159
Slow Mode Divider Register (SLOW) . . . . . . . . . . . . . . . . . . .161
Real-Time Interrupt Control Register (RTICTL) . . . . . . . . . . .162
Real-Time Interrupt Flag Register (RTIFLG) . . . . . . . . . . . . .163
COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .164
Arm/Reset COP Timer Register (COPRST). . . . . . . . . . . . . .166