MC68HC11P2
MOTOROLA
vii
TABLE OF CONTENTS
Paragraph
Number
Page
Number
Title
10
RESETS AND INTERRUPTS
10.1
Resets .................................................................................................................10-1
10.1.1
Power-on reset ...............................................................................................10-1
10.1.2
External reset (RESET) .................................................................................10-2
10.1.3
COP reset ......................................................................................................10-2
10.1.4
Clock monitor reset ........................................................................................10-3
10.1.5
OPTION — System conguration options register 1 .....................................10-3
10.1.6
CONFIG — Conguration control register ....................................................10-5
10.2
Effects of reset.....................................................................................................10-6
10.2.1
Central processing unit ..................................................................................10-6
10.2.2
Memory map ..................................................................................................10-6
10.2.3
Parallel I/O .....................................................................................................10-7
10.2.4
Timer..............................................................................................................10-7
10.2.5
Real-time interrupt (RTI) ................................................................................10-7
10.2.6
Pulse accumulator .........................................................................................10-7
10.2.7
Computer operating properly (COP) ..............................................................10-7
10.2.8
Serial communications interface (SCI)...........................................................10-8
10.2.9
Serial peripheral interface (SPI) .....................................................................10-8
10.2.10
Analog-to-digital converter .............................................................................10-8
10.2.11
System ...........................................................................................................10-8
10.3
Reset and interrupt priority ..................................................................................10-9
10.3.1
HPRIO — Highest priority I-bit interrupt and misc. register ...........................10-10
10.4
Interrupts .............................................................................................................10-13
10.4.1
Interrupt recognition and register stacking .....................................................10-13
10.4.2
Nonmaskable interrupt request (XIRQ)..........................................................10-14
10.4.3
Illegal opcode trap..........................................................................................10-14
10.4.4
Software interrupt...........................................................................................10-14
10.4.5
Maskable interrupts........................................................................................10-15
10.4.6
Reset and interrupt processing ......................................................................10-15
10.5
Low power operation ...........................................................................................10-15
10.5.1
WAIT ..............................................................................................................10-15
10.5.2
STOP .............................................................................................................10-16