AN1215/D
MOTOROLA
9
Although the sampling period constant and the constants of each term of the PID algorithm could be calcu-
lated during the assembly phase and set in the final code, these values are instead initialized as ratios of
hexadecimal integers, then calculated in real time in the loop. This arrangement allows easy experimenta-
tion with these values without reassembling each time a value is changed. The initial format of these values
(numerator and denominator) is a consequence of the four-byte numeric representation.
Here are some examples of ALU operations performed during PID computation.
To perform a signed integer divide followed by a signed fractional divide, the numerator is written to
CREG, $C0 is written to ALUC, and the divisor is written to AREG. After the completion flag in ALUF is
set ($49), $E8 is written to ALUC. Following integer division, the quotient is in CREG and the remainder
is in BREG. Fractional division moves the content of CREG Low to CREG High, then places a 16-bit
fraction in CREG Low. The final result is a 16-bit quotient in CREG High and a 16-bit fraction in CREG
Low. There is an implicit decimal point between CREG High and CREG Low. More precision can be
obtained by concatenating fractional divisions.
To perform a signed multiply, $80 is written to ALUC and multiplicands are written to AREG and BREG.
When the operation is complete, a 32-bit result is in CREG.
The actual range used for control is hexadecimal $0000.0000 to $00FF.FFFF (decimal 0 to 255.99998).
While the error term can be positive or negative, PWM output and feedback voltage are always positive. A
result greater than $FF is treated as an overflow, and a result less than $00 is treated as an underflow. This
effects a saturated value of the correct sign as in the C version. Except for the expression of initial constants
as ratios, formula 5 is not changed. In the derivative term the factor
(KDNUM / KDDEN) / ((6
(PERDTNUM / PERDTDEN))
is rearranged to
((KDNUM / KDDEN)
PERDTDEN) / (6
PERDTNUM).
The DOPID routine is written as straight-line code. Only two subroutines and a limit-checking section are
shared by the proportional, integral, and derivative terms. The subroutines MULLNG and ADLNG are used
to multiply and add terms and factors expressed in the special four-byte format explained previously. Each
of the P, I, and D terms use ADLNG to contribute to the new PWM duty cycle (NEWDTY), but, as in the C
version of the PID routine, NEWDTY is not output until the beginning of the next period. Only the
8-bit integer portion is used, and the 1-bit round-off error this causes is not corrected — the effect is negli-
gible in this 8-bit example. After all three terms are calculated, control is returned to the master C routine.
The master routine updates the error and A to D pipelines, then enters the main wait loop.
During program execution, all results and most intermediate values are kept in RAM, rather than on the
stack. Controller state can easily be inspected by means of a single breakpoint and a dump of the appropri-
ate variable address. Variable addresses are provided in the C startup code for the assembly routine — the
addresses are only valid for this compilation and can change with code revision.
HARDWARE PLATFORM
The Motorola M68HC11KMNPEVS Evaluation System can be used to run both versions of the PID routine.
With an MC68HC11K4 inserted in the emulator module, only the floating point version will execute. With an
MC68HC11N4 inserted, both versions can be executed — the floating point version simply does not use the
math coprocessor.
Both versions of the PID routine utilize special test mode in the EVS system. This means that the M68HC11
processor vectors are mapped from $BFD6 to $BFFF instead of from $FFD6 to $FFFF, and can be placed
in user RAM or in emulation RAM, making experimentation with varied processor configuration options eas-
ier. Refer to the
M68HC11KMNPEVS Evaluation System User's Manual
for more information.