MOTOROLA
4
AN1215/D
The main program initializes constants and variables, sets up the required on-chip peripherals, and waits
for interrupts to occur. The M68HC11 real-time interrupt (RTI) is used to establish a precise time base for
performing PID compensation. The period (T or PERDT) is determined by the RTI rate. In these examples,
the period is 16.383 milliseconds, but this value is arbitrary — in real applications, the performance of the
controlling microprocessor and the requirements of the controlled system determine the period.
The RTI_interrupt function is a workhorse. It does PID loop PWM duty cycle calculations, performs I/O using
the DOIO assembly language function, and checks the results against the usable PWM output range of $00
to $FF. If a floating-point result is out of range, the closest limit is substituted. This “saturation arithmetic”
prevents out-of-range results from causing sign-reversals in the PWM output.
Details of error-checking and the DOIO subroutine are best understood by looking at the format of the float-
ing-point variables. The four byte format is:
SEEEEEEE EMMMMMMM MMMMMMMM MMMMMMMM
S represents a sign bit, E represents an 8-bit exponent biased by 127, and M represents a 23-bit fractional
mantissa (significand) with an implicit leading 1. The I/O range of $00 to $FF is scaled into the eight most
significant bits of a floating-point variable, giving a floating-point range of 1.0 ($3F800000) to 1.998046875
($3FFF8000). The following expression is used to evaluate a floating-point number:
F = [(-1)
S
] [2
(E-127)]
[1.M]
When the RTI_interrupt function returns control to the C routine, the last task the routine must perform is
preparation for the next period. A two-element pipeline of the A/D reading and a four-element error pipeline
are updated. Finally the “old” duty cycle value is copied into OLDDTY.
MC68HC11N4 MATH COPROCESSOR
The assembly PID routine uses the MC68HC11N4 math coprocessor, which is commonly referred to as an
arithmetic logic unit, or ALU. The ALU performs 32/16-bit division, 16/16 multiplication, multiply-and-accu-
mulate operations, and 16/16-bit fractional division without CPU intervention. As
processor has one control register, one status register, and three data registers. Arrows indicate the most
convenient order of writing the registers.
Figure 2
shows, the co-
Figure 2 Coprocessor Registers and Operations
32 BITS
8 BITS
16 BITS
16 BITS
$_040
$_044
$_045
$_047
MAC
DIV
MUL
FDIV
START
MULTIPLY
START
DIVISION
START
FDIV
ALU REGISTERS
$_048
$_046
AREG
BREG
(CREG HIGH)
CREG
(CREG LOW)
ALUC
$_049
8 BITS
ALUF
$_041
$_042
$_043
COPROCESSAN1215