MC68HC11KW1
MOTOROLA
iii
TABLE OF CONTENTS
Paragraph
Number
Page
Number
TITLE
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.3.2.5
4.3.2.6
4.3.2.7
4.3.2.8
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.5.1
4.5.5.2
4.5.5.3
4.5.5.4
4.5.6
4.5.7
4.5.7.1
4.6
4.6.1
4.6.1.1
4.6.1.2
4.6.1.3
4.6.1.4
4.6.2
4.6.3
Initialization ......................................................................................................4-12
CONFIG — System configuration register.................................................4-12
INIT — RAM and I/O mapping register ......................................................4-13
INIT2 — EEPROM mapping register..........................................................4-15
OPTION — System configuration options register 1..................................4-15
OPT2 — System configuration options register 2......................................4-17
BPROT — Block protect register................................................................4-18
TMSK2 — Timer interrupt mask register 2.................................................4-20
TCTL4 and TCTL6 — Timer 2 and 3 control registers ...............................4-21
Memory expansion ................................................................................................4-22
Memory expansion logic ..................................................................................4-22
Extended addressing.......................................................................................4-23
Memory expansion examples ..........................................................................4-24
MMSIZ — Memory mapping window size register...........................................4-29
MMWBR – Memory mapping window base register........................................4-30
MM1CR, MM2CR – Memory mapping window 1 and 2 control registers........4-31
PGAR — Port G assignment register ..............................................................4-32
Chip selects...........................................................................................................4-32
Chip select priorities.........................................................................................4-33
Program chip select .........................................................................................4-33
I/O chip select ..................................................................................................4-33
CSCTL — Chip select control register.............................................................4-34
General-purpose chip selects..........................................................................4-35
GPCS1A — General-purpose chip select 1 address register ....................4-35
GPCS1C — General-purpose chip select 1 control register......................4-36
GPCS2A — General-purpose chip select 2 address register ....................4-37
GPCS2C — General-purpose chip select 2 control register......................4-37
One chip select driving another .......................................................................4-38
Clock stretching ...............................................................................................4-39
CSCSTR — Chip select clock stretch register ...........................................4-39
EEPROM and CONFIG register............................................................................4-41
EEPROM .........................................................................................................4-41
PPROG — EEPROM programming control register ..................................4-41
EEPROM bulk erase ..................................................................................4-43
EEPROM row erase...................................................................................4-43
EEPROM byte erase..................................................................................4-44
CONFIG register programming........................................................................4-44
RAM and EEPROM security............................................................................4-45
5
RESETS AND INTERRUPTS
5.1
5.1.1
5.1.2
Resets ...................................................................................................................5-1
Power-on reset.................................................................................................5-1
External reset (RESET) ...................................................................................5-2
TPG
5