MOTOROLA
viii
MC68HC11KW1
INDEX
control registers
4-31
MMSIZ — Memory mapping window size register
4-29
MMWBR — Memory mapping window base register
4-30
PGAR — Port G assignment register
4-32
memory map, on reset
5-7
MISO
8-4
MM1CR, MM2CR — Memory mapping window 1 and 2
control registers
4-31
MMSIZ — Memory mapping window size register
4-29
MMWBR — Memory mapping window base register
4-30
MODA/LIR pin
2-5
MODB/VSTBY pin
2-5
MODF - bit in SPSR
8-8
MOSI
8-4
MSTR - bit in SPCR
8-5
,
8-6
MULT — bit in ADCTL
10-7
MXGS[2:1] - bits in MMSIZ
4-29
N
N-bit in CCR
3-5
NF - bit in SCSR1
7-11
NMI
2-5
5-14
NOCOP - bit in CONFIG
5-6
noise
2-4
non-maskable interrupt
2-5
NOSEC - bit in CONFIG
4-46
O
OC1D — Output compare 1 data register
9-10
OC1D[7:3] - bits in OC1D
9-10
OC1F–OC3F - bits in T2FLG
9-23
OC1F–OC3F - bits in T3FLG
9-30
OC1F–OC4F - bits in TFLG1
9-13
OC1I–OC3I - bits in T2MSK
9-22
OC1I–OC3I - bits in T3MSK
9-29
OC1I–OC4I - bits in TMSK1
9-12
OC1M — Output compare 1 mask register
9-10
OC1M[7:3] - bits in OC1M
9-10
ODD - bit in PPROG
4-41
OL[1:4] - bits in TCTL3
9-20
OL[1:4] - bits in TCTL5
9-27
OL[2:5] - bits in TCTL1
9-11
OM[1:4] - bits in TCTL3
9-20
OM[1:4] - bits in TCTL5
9-27
OM[2:5] - bits in TCTL1
9-11
operating modes
4-1
baud rates
4-2
bootstrap
4-2
expanded
4-1
HPRIO register
4-11
selection of
2-5
,
4-10
single chip
4-1
STOP
4-4
,
5-16
test
4-2
VSTBY
4-4
WAIT
5-15
OPT2 — System configuration options reg. 2
4-17
OPTION — System configuration options reg. 1
5-4
OR - bit in SCSR1
7-11
oscillator
2-3
connections
2-3
output compare
9-8
overflow bit in CCR
3-5
P
packages
options
2-1
,
B-1
thermal characteristics
A-1
PACNT — Pulse accumulator count reg.
9-36
PACTL — Pulse accumulator control reg.
9-35
PAEN - bit in PACTL
9-35
PAIF - bit in TFLG2
9-37
PAII - bit in TMSK2
9-37
PAMOD - bit in PACTL
9-35
PAOVF - bit in TFLG2
9-36
PAOVI - bit in TMSK2
9-36
PAREN - bit in CONFIG
6-15
PCKA[2:1] - bits in PWCLK
9-40
PCKB[3:1] - bits in PWCLK
9-40
PCLK[2:1] - bits in PWPOL
9-41
PCLK[4:3] - bits in PWPOL
9-41
PCSA, PCSB - bits in CSCSTR
4-39
PCSEN - bit in CSCTL
4-34
PCSZA, PCSZB - bits in CSCTL
4-34
PE - bit in SCCR1
7-8
PEDGE - bit in PACTL
9-35
PF - bit in SCSR1
7-11
PGAR — Port G assignment register
4-32
PGAR[5:0] - bits in PGAR
4-32
pins
E clock
2-4
EXTAL
2-3
IRQ
2-4
LIR
2-5
MODA/LIR
2-5
MODB/VSTBY
2-5
OC1, special features
9-4
,
9-8
R/W
2-6
RESET
2-2
,
5-2
VDD AD, VSS AD
2-4
VDD, VSS
2-4
VRH, VRL
2-6
VSTBY
2-5
XIRQ
2-5
XOUT
2-4
XTAL
2-3
POR
5-1
PORTA — Port A data reg.
6-2
PORTB — Port B data reg.
6-3
PORTC — Port C data reg.
6-4
PORTD — Port D data reg.
6-5
PORTE — Port E data reg.
6-6
TPG
230