
Operating Modes and On-Chip Memory
Memory Map
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Operating Modes and On-Chip Memory
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In expanded modes, the ROM/EPROM/OTPROM (if present) is enabled out of 
reset and located at the top of the memory map if the ROMON bit in the CONFIG 
register is set. ROM or EPROM is enabled out of reset in single-chip and bootstrap 
modes, regardless of the state of ROMON. 
For devices with 512 bytes of EEPROM, the EEPROM is located at $B600–$B7FF 
and has the same read cycle time as the internal ROM. The 512 bytes of EEPROM 
cannot be remapped to other locations. 
For the MC68HC811E2, EEPROM is located at $F800–$FFFF and can be 
remapped to any 4-Kbyte boundary. EEPROM mapping control bits (EE[3:0] in 
CONFIG) determine the location of the 2048 bytes of EEPROM and are present 
only on the MC68HC811E2. Refer to 
2.3.3.1 System Configuration Register
 for 
a description of the MC68HC811E2 CONFIG register. 
EEPROM can be programmed or erased by software and an on-chip charge pump, 
allowing EEPROM changes using the single V
DD
 supply. 
2.3.2  Mode Selection 
The four mode variations are selected by the logic states of the MODA and MODB 
pins during reset. The MODA and MODB logic levels determine the logic state of 
SMOD and the MDA control bits in the highest priority I-bit interrupt and 
miscellaneous (HPRIO) register. 
After reset is released, the mode select pins no longer influence the MCU operating 
mode. In single-chip operating mode, the MODA pin is connected to a logic level 0. 
In expanded mode, MODA is normally connected to V
DD
 through a pullup resistor 
of 4.7 k
. The MODA pin also functions as the load instruction register LIR pin 
when the MCU is not in reset. The open-drain active low LIR output pin drives low 
during the first E cycle of each instruction. The MODB pin also functions as standby 
power input (V
STBY
), which allows RAM contents to be maintained in absence of 
V
DD
. 
Refer to 
Table 2-1
, which is a summary of mode pin operation, the mode control 
bits, and the four operating modes.
Table 2-1. Hardware Mode Select Summary 
Input Levels
at Reset
Mode
Control Bits in HPRIO
(Latched at Reset) 
MODB
MODA
RBOOT
SMOD
 MDA 
1
0
Single chip
0
0
0 
1
1
Expanded
0
0
1 
0
0
Bootstrap
1
1
0 
0
1
Special test
0
1
1 
F
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n
.