參數(shù)資料
型號: MC68HC11D3CFN2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 135/138頁
文件大?。?/td> 1047K
代理商: MC68HC11D3CFN2
Programmable Timer
MC68HC711D3 Data Sheet, Rev. 2.1
96
Freescale Semiconductor
8.4.8 Timer Interrupt Flag 1 Register
The timer interrupt flag 1 register (TFLG1) bits indicate when timer system events have occurred. Coupled
with the bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either a polled or
interrupt driven system. Each bit of TFLG1 corresponds to a bit in TMSK1 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
OC1F–OC5F — Output Compare x Flag
Set each time the counter matches output compare x value
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL
IC1F–IC3F — Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line
8.4.9 Timer Interrupt Mask 2 Register
The timer interrupt mask 1 register (TMSK2) is an 8-bit register used to enable or inhibit timer overflow
and real-time interrupts. The timer prescaler control bits are included in this register.
TOI — Timer Overflow Interrupt Enable Bit
0 = TOF interrupts disabled
1 = Interrupt requested when TOF is set to 1
RTII — Real-Time Interrupt Enable Bit
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
PAII — Pulse Accumulator Input Edge Interrupt Enable Bit
NOTE
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2
enable the corresponding interrupt sources.
Address:
$0023
Bit 7
654321
Bit 0
Read:
OC1F
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
Write:
Reset:
00000000
Figure 8-13. Timer Interrupt Flag 1 Register (TFLG1)
Address:
$0024
Bit 7
654321
Bit 0
Read:
TOI
RTII
PAOVI
PAII
0
PR1
PR0
Write:
Reset:
00000000
Figure 8-14. Timer Interrupt Mask 2 Register (TMSK2)
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