參數(shù)資料
型號(hào)： MC68HC11A8BVP2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48
封裝： DIP-48
文件頁數(shù)： 9/158頁
文件大?。?/td> 776K
代理商： MC68HC11A8BVP2
MC68HC11A8
TECHNICAL DATA
MOTOROLA
ix
LIST OF ILLUSTRATIONS
Figure
1-1
1-2
2-1
2-2
2-3
2-4
3-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
6-1
6-2
6-3
7-1
7-2
9-1
9-2
9-3
9-4
9-4
9-5
9-5
9-6
10-1
10-2
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
A-11
A-12
A-13
(STRA Enables Output Buffer) A-16
A-14
Multiplexed Expansion Bus Timing Diagram ................................................A-21
A-8
a) SPI Master Timing (CPHA = 0) ................................................................A-24
Page
Block Diagram ................................................................................................ 1-2
Programming Model ....................................................................................... 1-3
Common Crystal Connections ........................................................................ 2-2
External Oscillator Connections ..................................................................... 2-2
One Crystal Driving Two MCUs ..................................................................... 2-2
Address/Data Demultiplexing ......................................................................... 2-8
Memory Maps ................................................................................................. 3-1
Data Format ................................................................................................... 5-2
Sampling Technique Used on All Bits ............................................................ 5-3
Examples of Start Bit Sampling Techniques .................................................. 5-4
SCI Artificial Start Following a Framing Error ................................................. 5-4
SCI Start Bit Following a Break ...................................................................... 5-4
Serial Communications Interface Block Diagram ........................................... 5-7
Rate Generator Division ............................................................................... 5-12
Data Clock Timing Diagram ........................................................................... 6-2
Serial Peripheral Interface Block Diagram ..................................................... 6-3
Serial Peripheral Interface Master-Slave Interconnection .............................. 6-4
A/D Conversion Sequence ............................................................................. 7-2
A/D Pin Model ................................................................................................ 7-2
Reset Timing .................................................................................................. 9-2
Simple LVI Reset Circuit ................................................................................ 9-3
Interrupt Stacking Order ................................................................................. 9-9
Processing Flow Out of Resets (Sheet 1 of 2) ............................................. 9-12
Processing Flow Out of Resets (Sheet 2 of 2) ............................................. 9-13
Interrupt Priority Resolution (Sheet 1 of 2) ................................................... 9-14
Interrupt Priority Resolution (Sheet 2 of 2) ................................................... 9-15
Interrupt Source Resolution Within SCI ........................................................ 9-16
Programming Model ..................................................................................... 10-2
Special Operations ..................................................................................... 10-12
Test Methods ..................................................................................................A-4
Timer Inputs ...................................................................................................A-7
POR and External Reset Timing Diagram ......................................................A-8
STOP Recovery Timing Diagram ...................................................................A-9
WAIT Recovery Timing Diagram ..................................................................A-10
Interrupt Timing Diagram ..............................................................................A-11
Port Write Timing Diagram ...........................................................................A-14
Port Read Timing Diagram ...........................................................................A-14
Simple Output Strobe Timing Diagram .........................................................A-14
Simple Input Strobe Timing Diagram ...........................................................A-15
Port C Input Handshake Timing Diagram .....................................................A-15
Port C Output Handshake Timing Diagram ..................................................A-15
Three-State Variation of Output Handshake Timing Diagram
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