參數(shù)資料
型號： MC68HC11A8BVP2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48
封裝： DIP-48
文件頁數(shù)： 88/158頁
文件大?。?/td> 776K
代理商： MC68HC11A8BVP2
MOTOROLA
9-8
RESETS, INTERRUPTS, AND LOW POWER MODES
MC68HC11A8
TECHNICAL DATA
9
into two basic categories, maskable and non-maskable. In the MC68HC11A8 fifteen
of the interrupts can be masked using the condition code register I bit. In addition to
being maskable by the I bit in the condition code register, all of the on-chip interrupt
sources are individually maskable by local control bits.
The software interrupt (SWI instruction) is a non-maskable instruction rather than a
maskable interrupt source. The illegal opcode interrupt is a non-maskable interrupt.
The last interrupt source, external input to the XIRQ pin, is considered a non-maskable
interrupt because once enabled, it cannot be masked by software; however, it is
masked during reset and upon receipt of an interrupt at the XIRQ pin.
Table 9-2
,
Table
9-3
, and
Table 9-4
provide a list of each interrupt, its vector location in memory, and
the actual condition code and control bits that mask it. A discussion of the various in-
terrupts is provided below.
Figure 9-3
shows the interrupt stacking order.
Table 9-2 IRQ Vector Interrupts
Interrupt Cause
External Pin
Parallel l/O Handshake
Local Mask
None
STAI
Table 9-3 Interrupt Vector Assignments
Vector
Address
FFC0, C1
FFD4, D5
FFD6, D7
FFD8, D9
FFDA, DB
FFDC, DD
FFDE, DF
FFE0, E1
FFE2, E3
FFE4, E5
FFE6, E7
FFE8, E9
FFEA, EB
FFEC, ED
FFEE, EF
FFF0, F1
FFF2, F3
FFF4, F5
FFF6, F7
FFF8, F9
FFFA, FB
FFFC, FD
FFFE, FF
Interrupt Source
CC
Local Mask
Register Mask
—
Reserved
Reserved
SCI Serial System
SPI Serial Transfer Complete
Pulse Accumulator Input Edge
Pulse Accumulator Overflow
Timer Overflow
Timer Output Compare 5
Timer Output Compare 4
Timer Output Compare 3
Timer Output Compare 2
Timer Output Compare 1
Timer Input Capture 3
Timer Input Capture 2
Timer Input Capture 1
Real Time Interrupt
IRQ (External Pin or Parallel l/O)
XIRQ Pin (Pseudo Non-Maskable Interrupt)
SWI
Illegal Opcode Trap
COP Failure (Reset)
COP Clock Monitor Fail (Reset)
RESET
—
—
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
X Bit
None
None
None
None
None
—
See Table 9-3
SPIE
PAII
PAOVI
TOI
OC5I
OC4I
OC3I
OC2I
OC1I
OC3I
OC2I
OC1I
RTII
See Table 9-4
None
None
None
NOCOP
CME
None
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