參數(shù)資料
型號(hào)： MC68HC11A8BVP2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48
封裝： DIP-48
文件頁數(shù)： 133/158頁
文件大?。?/td> 776K
代理商： MC68HC11A8BVP2
MC68HC11A8
TECHNICAL DATA
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-13
A
NOTES:
1.If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one
more cycle.
2.Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respec-
tively).
3.All timing is shown with respect to 20% V
DD
and 70% V
DD
, unless otherwise noted.
Table A-5a Peripheral Port Timing (MC68L11A8)
V
DD
= 3.0 Vdc to 5.5 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
Characteristic
Symbol
1.0 MHz
Min
dc
1000
100
2.0 MHz
Min
dc
500
100
Unit
Max
1.0
—
—
Max
2.0
—
—
Frequency of Operation (E-Clock Frequency)
E-Clock Period
Peripheral Data Setup Time
(MCU Read of Ports A, C, D, and E)
Peripheral Data Hold Time
(MCU Read of Ports A, C, D, and E)
Delay Time, Peripheral Data Write
MCU Write to Port A
MCU Writes to Ports B, C, and D
t
PWD
= 1/4 t
cyc
+ 150 ns
Input Data Setup Time (Port C)
Input Data Hold Time (Port C)
Delay Time, E Fall to STRB
Setup Time, STRA Asserted to E Fall (Note 1)
Delay Time, STRA Asserted to Port C Data Output Valid
Hold Time, STRA Negated to Port C Data
Three-State Hold Time
f
o
MHz
ns
ns
t
cyc
t
PDSU
t
PDH
50
—
50
—
ns
t
PWD
—
—
60
100
—
0
—
10
—
250
400
—
—
400
—
100
—
150
—
—
60
100
—
0
—
10
—
250
275
—
—
275
—
100
—
150
ns
t
IS
t
IH
t
DEB
t
AES
t
PCD
t
PCH
t
PCZ
ns
ns
ns
ns
ns
ns
ns
t
DEB
= 1/4 t
cyc
+ 150 ns
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