參數(shù)資料
型號： MC68HC11A8BCFN2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 31/158頁
文件大?。?/td> 776K
代理商： MC68HC11A8BCFN2
MC68HC11A8
TECHNICAL DATA
ON-CHIP MEMORY
MOTOROLA
3-5
3
Note that if the RAM is relocated to either $E000 or $F000, which is in conflict with the
internal ROM, (no conflict if the ROMON bit in the configuration register is zero), RAM
will take priority and the conflicting ROM will become inaccessible. Also, if the 64 con-
trol registers are relocated so that they conflict with the RAM and/or ROM, then the 64
control registers take priority and the RAM and/or ROM at those locations become in-
accessible. No harmful conflicts result, the lower priority resources simply become in-
accessible. Similarly, if an internal resource conflicts with an external device no
harmful conflict results. Data from the external device will not be applied to the internal
data bus and cannot interfere with the internal read.
Note that there are unused register locations in the 64 byte control register block.
Reads of these unused registers will return data from the undriven internal data bus
and not from another resource that happens to be located at the same address.
3.3 ROM
The internal 8K ROM occupies the highest 8K of the memory map ($E000–$FFFF).
This ROM is disabled when the ROMON bit in the CONFIG register is clear. The
ROMON bit is implemented with an EEPROM cell and is programmed using the same
procedures for programming the on-chip EEPROM. For further information refer to
3.5.3 System Configuration Register (CONFIG)
.
In the single-chip operating mode, internal ROM is enabled regardless of the state of
the ROMON bit.
There is also a 192 byte mask programmed boot ROM in the MC68HC11A8. This
bootstrap program ROM controls the operation of the special bootstrap operating
mode and is only enabled following reset in the special bootstrap operating mode. For
more information refer to
2.2.3 Special Bootstrap Operating Mode.
3.4 RAM
The 256 byte internal RAM may be relocated during initialization by writing to the INIT
register. The reset default position is $0000 through $00FF. This RAM is implemented
with static cells and retains its contents during the WAIT and STOP modes.
The contents of the 256-byte RAM can also be retained by supplying a low current
backup power source to the MODB/V
STBY
pin. When using a standby power source,
V
DD
may be removed; however, RESET must go low before V
DD
is removed and re-
main low until V
DD
has been restored.
3.5 EEPROM
The 512 bytes of EEPROM are located at $B600 through $B7FF and have the same
read cycle time as the internal ROM. The write (or programming) mechanism for the
EEPROM is controlled by the PPROG register. The EEPROM is disabled when the
EEON bit in the CONFIG register is zero. The EEON bit is implemented with an EE-
PROM cell.
相關PDF資料
PDF描述
MC68HC11A8BCFU2 HCMOS Single-Chip Microcontroller
MC68HC11A8BCP2 HCMOS Single-Chip Microcontroller
MC68HC11A8BMP2 HCMOS Single-Chip Microcontroller
MC68HC11A8BVP2 HCMOS Single-Chip Microcontroller
MC68HC11A1CFN2 HCMOS Single-Chip Microcontroller
相關代理商/技術參數(shù)
參數(shù)描述
MC68HC11A8BCFU2 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller
MC68HC11A8BCP2 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller
MC68HC11A8BMP2 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller
MC68HC11A8BVP2 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller
MC68HC11A8FN 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontrollers
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