Memory Map
Monitor ROM
MC68HC908JB8MC68HC08JB8MC68HC08JT8 — Rev. 2.3
Technical Data
Freescale Semiconductor
Memory Map
45
$001E
IRQ Status and Control
Register
(ISCR)
Read:
0
0
0
0
IRQF
0
IMASK
MODE
Write:
ACK
Reset:
0
0
0
0
0
0
0
0
$001F
Configuration Register
(CONFIG)
Read:
0
0
URSTD
LVID
SSREC
COPRS
STOP
COPD
Write:
Reset:
0
0
0
0
0
0
0
0
One-time writable register after each reset. URSTD and LVID bits are reset by POR or LVI reset only.
$0020
USB Endpoint 0 Data
Register 0
(UE0D0)
Read: UE0R07
UE0R06
UE0R05
UE0R04
UE0R03
UE0R02
UE0R01
UE0R00
Write: UE0T07
UE0T06
UE0T05
UE0T04
UE0T03
UE0T02
UE0T01
UE0T00
Reset:
Unaffected by reset
$0021
USB Endpoint 0 Data
Register 1
(UE0D1)
Read: UE0R17
UE0R16
UE0R15
UE0R14
UE0R13
UE0R12
UE0R11
UE0R10
Write: UE0T17
UE0T16
UE0T15
UE0T14
UE0T13
UE0T12
UE0T11
UE0T10
Reset:
Unaffected by reset
$0022
USB Endpoint 0 Data
Register 2
(UE0D2)
Read: UE0R27
UE0R26
UE0R25
UE0R24
UE0R23
UE0R22
UE0R21
UE0R20
Write: UE0T27
UE0T26
UE0T25
UE0T24
UE0T23
UE0T22
UE0T20
Reset:
Unaffected by reset
$0023
USB Endpoint 0 Data
Register 3
(UE0D3)
Read: UE0R37
UE0R36
UE0R35
UE0R34
UE0R33
UE0R32
UE0R31
UE0R30
Write: UE0T37
UE0T36
UE0T35
UE0T34
UE0T33
UE0T32
UE0T31
UE0T30
Reset:
Unaffected by reset
$0024
USB Endpoint 0 Data
Register 4
(UE0D4)
Read: UE0R47
UE0R46
UE0R45
UE0R44
UE0R43
UE0R42
UE0R41
UE0R40
Write: UE0T47
UE0T46
UE0T45
UE0T44
UE0T43
UE0T42
UE0T41
UE0T40
Reset:
Unaffected by reset
$0025
USB Endpoint 0 Data
Register 5
(UE0D5)
Read: UE0R57
UE0R56
UE0R55
UE0R54
UE0R53
UE0R52
UE0R51
UE0R50
Write: UE0T57
UE0T56
UE0T55
UE0T54
UE0T53
UE0T52
UE0T51
UE0T50
Reset:
Unaffected by reset
$0026
USB Endpoint 0 Data
Register 6
(UE0D6)
Read: UE0R67
UE0R66
UE0R65
UE0R64
UE0R63
UE0R62
UE0R61
UE0R60
Write: UE0T67
UE0T66
UE0T65
UE0T64
UE0T63
UE0T62
UE0T61
UE0T60
Reset:
Unaffected by reset
$0027
USB Endpoint 0 Data
Register 7
(UE0D7)
Read: UE0R77
UE0R76
UE0R75
UE0R74
UE0R73
UE0R72
UE0R71
UE0R70
Write: UE0T77
UE0T76
UE0T75
UE0T74
UE0T73
UE0T72
UE0T71
UE0T70
Reset:
Unaffected by reset
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
=Unimplemented
R
=Reserved
U=Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)