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| 型號(hào)： | MC68HC08AS32AVFU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers |
| 中文描述： | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 72/296頁(yè) |
| 文件大小： | 2291K |
| 代理商： | MC68HC08AS32AVFU |
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Byte Data Link Controller-Digital (BDLC-D)
Data Sheet
MC68HC08AS32A — Rev. 1
72
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
EOF — End-of-Frame Symbol
This symbol is a long 280-
μ
s passive period on the J1850 bus and is longer than
an end-of-data (EOD) symbol, which signifies the end of a message. Since an
EOF symbol is longer than a 200-
μ
s EOD symbol, if no response is transmitted
after an EOD symbol, it becomes an EOF, and the message is assumed to be
completed. The EOF flag is set upon receiving the EOF symbol.
IFS — Inter-Frame Separation Symbol
The IFS symbol is a 20-
μ
s passive period on the J1850 bus which allows proper
synchronization between nodes during continuous message transmission. The
IFS symbol is transmitted by a node after the completion of the end-of-frame
(EOF) period and, therefore, is seen as a 300-
μ
s passive period.
When the last byte of a message has been transmitted onto the J1850 bus and
the EOF symbol time has expired, all nodes then must wait for the IFS symbol
time to expire before transmitting a start-of-frame (SOF) symbol, marking the
beginning of another message.
However, if the BDLC is waiting for the IFS period to expire before beginning a
transmission and a rising edge is detected before the IFS time has expired, it
will synchronize internally to that edge. If a write to the BDR register (for
instance, to initiate transmission) occurred on or before 104 t
BDLC
from the
received rising edge, then the BDLC will transmit and arbitrate for the bus. If a
CPU write to the BDR register occurred after 104 t
BDLC
from the detection of
the rising edge, then the BDLC will not transmit, but will wait for the next IFS
period to expire before attempting to transmit the byte.
A rising edge may occur during the IFS period because of varying clock
tolerances and loading of the J1850 bus, causing different nodes to observe the
completion of the IFS period at different times. To allow for individual clock
tolerances, receivers must synchronize to any SOF occurring during an IFS
period.
BREAK — Break
The BDLC cannot transmit a BREAK symbol.
If the BDLC is transmitting at the time a BREAK is detected, it treats the BREAK
as if a transmission error had occurred and halts transmission.
If the BDLC detects a BREAK symbol while receiving a message, it treats the
BREAK as a reception error and sets the invalid symbol flag in the BSVR, also
ignoring the frame it was receiving. If while receiving a message in 4X mode,
the BDLC detects a BREAK symbol, it treats the BREAK as a reception error,
sets the invalid symbol flag, and exits 4X mode (for example, the RX4XE bit in
BCR2 is cleared automatically). If bus control is required after the BREAK
symbol is received and the IFS time has elapsed, the programmer must resend
the transmission byte using highest priority.
NOTE:
The J1850 protocol BREAK symbol is not related to the HC08 break module (see
17.2 Break Module (BRK)
)
F
Freescale Semiconductor, Inc.
n
.
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