參數(shù)資料
型號： MC68HC05X4CDWR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PDSO28
封裝： PLASTIC, SOIC-28
文件頁數(shù)： 144/168頁
文件大?。?/td> 656K
代理商： MC68HC05X4CDWR2
Motorola CAN
Interface to the MC68HC05X4 CPU
MC68HC05X4 Rev 1.0
MOTOROLA
Motorola CAN
77
9-mcan
MCAN control
register (CCNTRL)
This register may be read or written to by the MCU; only the RR bit is
affected by the MCAN.
NOTE:
Only the RR bit in this register can be written when the RR bit is set.
MODE — Undefined mode
This bit must never be set by the CPU as this would result in the
transmit and receive buffers being mapped out of memory. The bit is
cleared on reset, and should be left in this state for normal operation.
SPD — Speed mode
1 = Slow – Bus line transitions from both ‘recessive’ to ‘dominant’ and
from ‘dominant’ to ‘recessive’ will be used for resynchronization.
0 = Fast – Only transitions from ‘recessive’ to ‘dominant’ will be
used for resynchronization.
OIE — Overrun interrupt enable
1 = Enabled – The CPU will get an interrupt request whenever the
Overrun Status bit gets set.
0 = Disabled – The CPU will get no overrun interrupt request.
EIE — Error interrupt enable
1 = Enabled – The CPU will get an interrupt request whenever the
error status or bus status bits in the CSTAT register change.
0 = Disabled – The CPU will get no error interrupt request.
TIE — Transmit interrupt enable
1 = Enabled – The CPU will get an interrupt request whenever a
message has been successfully transmitted, or when the transmit
buffer is accessible again following an ABORT command.
0 = Disabled – The CPU will get no transmit interrupt request.
Address:
$0020
Bit 7
654321
Bit 0
MODE
SPD
OIE
EIE
TIE
RIE
RR
External Reset:
0
u
-
uuuu1
Reset: with RR bit set
0
u
-
uuuu1
Figure 4. MCAN Control Register (CCNTRL)
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