參數(shù)資料
型號: MC68HC05V7FN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 152/170頁
文件大?。?/td> 589K
代理商: MC68HC05V7FN
MOTOROLA
SECTION 10: A/D CONVERTER
Page 68
MC68HC05V7 Specification Rev. 1.0
10.6
A/D DURING WAIT MODE
The A/D converter continues normal operation during WAIT mode. To decrease power
consumption during WAIT, it is recommended that both the ADON and ADRC bits in the A/
D Status and Control Registers be cleared if the A/D converter is not being used. If the A/
D converter is in use and the system clock rate is above 1.0 MHz, it is recommended that
the ADRC bit be cleared.
NOTE:
As the A/D converter continues to function normally in WAIT mode, the
COCO bit is not cleared.
10.7
A/D DURING STOP MODE
In STOP mode the comparator and charge pump are turned off and the A/D ceases to
function. Any pending conversion is aborted. When the clocks begin oscillation upon
leaving the STOP mode, a finite amount of time passes before the A/D circuits stabilize
enough to provide conversions to the specified accuracy. Normally, the delays built into the
device when coming out of STOP mode are sufficient for this purpose, therefore no explicit
delays need to be built into the software.
NOTE:
Although the comparator and charge pump are disabled in STOP mode,
the A/D Data and Status/Control registers are not modified. Disabling the
A/D prior to entering STOP mode will not effect the STOP mode current
consumption.
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