參數(shù)資料
型號： MC68HC05V7FN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 150/170頁
文件大小： 589K
代理商： MC68HC05V7FN
MOTOROLA
SECTION 10: A/D CONVERTER
Page 66
MC68HC05V7 Specification Rev. 1.0
10.3.2
INTERNAL VS. MASTER OSCILLATOR
If the MCU bus (E clock) frequency is less than 1.0 MHz, an internal RC oscillator
(nominally 1.5 MHz) must be used for the A/D conversion clock. This selection is made by
setting the ADRC bit in the A/D Status and Control Registers to 1. In STOP mode, the
internal RC oscillator is turned off automatically, though the A/D subsystem remains
enabled (ADON remains set). In WAIT mode the A/D subsystem remains functional. See
When the internal RC oscillator is being used as the conversion clock, three limitations
apply:
1. The Conversion Complete Flag (COCO) must be used to determine when
a conversion sequence has been completed, due to the frequency
tolerance of the RC oscillator and its asynchronism with regard to the
MCU E clock.
2. The conversion process runs at the nominal 1.5 MHz rate but the
conversion results must be transferred to the MCU result registers
synchronously with the MCU E clock so conversion time is limited to a
maximum of one channel per E cycle.
3. If the system clock is running faster than the RC oscillator, the RC
oscillator should be turned off, and the system clock used as the
conversion clock.
10.3.3
MULTI-CHANNEL OPERATION
A multiplexer allows the A/D converter to select one of sixteen external analog signals and
four internal reference sources.
10.4
A/D STATUS AND CONTROL REGISTER (ADSCR)
The following paragraphs describe the function of the A/D Status and Control Register.
Figure 10-1:
A/D Status and Control Register
10.4.1
COCO - Conversions Complete
This read-only status bit is set when a conversion is completed, indicating that the A/D Data
Register contains valid results. This bit is cleared whenever the A/D Status and Control
Register is written and a new conversion is automatically started, or whenever the A/D Data
Register is read. Once a conversion has been started by writing to the A/D Status and
Control Register, conversions of the selected channel will continue every 32 cycles until the
A/D Status and Control Register is written again. In this continuous conversion mode the
A/D Data Register will be filled with new data, and the COCO bit set, every 32 cycles. Data
from the previous conversion will be overwritten regardless of the state of the COCO bit
prior to writing.
0
000000
0
RESET:
COCO
ADON
CH4
CH3
CH2
CH1
CH0
ADRC
$1E
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