MOTOROLA
8
AN1257/D
INTERNAL CONFIGURATION AND CONTROL OF THE POWER SUPPLY
The voltage regulation circuit on the MC68HC705V8 and MC68HC05V7 is controlled by the user through
several mask options and through one control bit and one status bit in a user register on each MCU. A
description follows of the mask options and the user register bits and how they affect the voltage regulator
operation. This description assumes the user is familiar with the implementation of user registers and mask
option registers on the M68HC05 Family.
Mask Options
Three mask options on the MC68HC705V8 and MC68HC05V7 affect the operation of the on-chip voltage
regulator. These mask options include voltage regulator enable/disable, enabling a V
DD
to V
SSD
clamp
when the primary regulator is in standby mode and re-enabling the primary regulator from standby mode
when a rising edge is detected at the BUS pin. An additional mask option is available to enable the LVR
circuit. The mask options are user-programmable on the EPROM-based MC68HC705V8 via the mask
option register (MOR, address $3C00) and are customer-selected at the time of ROM pattern submission
on the ROM-based MC68HC05V7. Each option is described here as programmed by the user on the
MC68HC705V8. For an illustration of the placement of the bits in the MOR register, refer to Figure 4.
Figure 4. MC68HC705V8 Mask Option Register
The REGEN bit (bit 6) in the MOR of the MC68HC705V8 is used to enable the on-chip voltage regulation
system. If this bit is programmed to a logic one, the primary voltage regulator will be enabled whenever the
minimum specified voltage necessary for proper regulator operation is applied to the V
BATT
pin and the
appropriate external conditions are detected by the MCU. In addition to the primary regulator, the REGEN
bit also enables the power moding function of the power supply control logic. If the REGEN bit is
programmed to a logic zero, the primary voltage regulator never will be enabled. In this case, the user must
supply 5 volts to both V
DD
pins of the MCU from an external power source. The secondary regulator always
will be enabled whenever the supply voltage to the V
BATT
pin is above the minimum operating voltage
specified for correct regulator operation, regardless of the state of the REGEN bit.
If the VDDC bit (bit 5) in the MOR is programmed to a logic one, an active device clamping V
DD
to V
SSD
will
be enabled whenever a logic zero is written to the PDC bit in the MISC register. (See Figure 5.) This helps
ensure that no devices (including the MCU) powered by the on-chip voltage regulator will be active as long
as the primary regulator remains in standby mode. The V
DD
to V
SSD
clamp will be released whenever the
external conditions necessary to enable the primary regulator are detected by the MCU (rising edge on
V
IGN
pin or optionally on BUS pin). If the VDDC bit is programmed to a logic zero, the active V
DD
to V
SSD
Bit 7
6
5
4
3
2
1
Bit 0
MOR
$3C00
Read:
0
REGEN
VDDC
MDLCPU
LVR
STOPEN
IRQ
COPEN
Write:
Reset:
Unaffected by reset
= Unimplemented
NOTES:
1. Bit 7 of the MOR is not implemented on the MC68HC705V8.
2. Bits 2-0 are mask options which do not affect operation of the on-chip voltage regulator or the LVR
circuitry.