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參數(shù)資料
| 型號： | MC68HC05V7 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 295K |
| 代理商： | MC68HC05V7 |
AN1257/D
MOTOROLA
11
regulator will enter the normal operating mode and the regulator's 5-volt output will be applied internally to
the digital portion of the MCU circuitry and externally to the V
DD
pins. When the output voltage of the
primary regulator reaches the specified minimum V
DD
voltage level, the LVR circuit will place the device in
the reset state. Once the primary regulator output reaches the V
LVRR
threshold, the MCU, after a delay
equal to 4064 CPU bus clock cycles, will release the reset signal internally. If, at this point, the output of the
POR circuit connected to the RST pin has not reached a valid V
IH
level, the device will remain in the reset
state. Once the voltage level at the RST pin does reach a valid V
IH
level, the MCU reset signal will be
released and the device will exit the reset state and begin normal operation.
During the MCU’s initialization sequence, which normally occurs immediately following an exit from the
reset state, the user should set the PDC bit in the MISC register to a logic one, since this bit is not
automatically set when the primary regulator exits the standby mode. This will prevent subsequent
read/modify/write instructions involving the MISC register from inadvertently returning the primary
regulator to standby mode.
Setting the PDC bit is the only software initialization necessary for proper operation of the on-chip voltage
regulator. Once this is done, the MCU can proceed with its normal initialization and application routines.
Refer to Figure 6 for an illustration of this voltage regulator initialization sequence.
Putting the Primary Regulator into Standby Mode
Once normal application processing is under way, the CPU can return the primary regulator to standby
mode at any time by writing a logic zero to the PDC bit in the MISC register. In the Figure 2 example, this
might be done whenever the IGNS bit in the MISC register is read as a logic zero, indicating that the
vehicle ignition has been switched off.
When a logic zero is written to the PDC bit, the primary regulator will go immediately into standby mode,
the V
DD
to V
SSD
clamp will be enabled, and the power consumption of the MCU will be reduced significantly.
Figure 7 illustrates the sequence which occurs when the primary regulator is put into standby mode by the
CPU through software.
Exiting Standby Mode
Once the primary voltage regulator has been put into the standby mode through software, it can only exit
the standby mode and return to the normal operating mode after the detection of a rising edge at the V
IGN
pin or, as in the automotive circuit example, following the detection of activity at the BUS pin. Once either of
these two events occurs, the primary regulator’s exit from standby mode is identical to the exit from
standby mode after a power-up of the MCU, so the same software routine can be used. Refer to Figure 8
for an illustration of this sequence.
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