參數(shù)資料
型號(hào)： MC68HC05T7B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝： SDIP-56
文件頁(yè)數(shù)： 80/109頁(yè)
文件大?。?/td> 9008K
代理商： MC68HC05T7B
Technical Data
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 3.0
70
Resets and Interrupts
MOTOROLA
Resets and Interrupts
triggered only or both positive-edge and high-level triggered. The
level-sensitive triggering option allows multiple external interrupt
sources to be wire-ORed to an external interrupt pin. An external
interrupt request, shown in Figure 5-5, is latched as long as any source
is holding an external interrupt pin low.
Figure 5-5. External Interrupt Timing
Table 5-2. External Interrupt Timing (VDD = 5.0 Vdc)
(1)
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
Characteristic
Symbol
Min
Max
Unit
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
Note(2)
2. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19
tcyc.
—
tcyc
Table 5-3. External Interrupt Timing (VDD = 3.3 Vdc)
(1)
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +85°C unless otherwise noted.
Characteristic
Symbol
Min
Max
Unit
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
250
—
ns
Interrupt Pulse Period
tILIL
Note(2)
2. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19
tcyc.
—
tcyc
IRQ
tILIH
tILIL
tILIH
EXT. INT. PIN
EXT. INT. PIN1
EXT. INT. PINn
.
(INTERNAL)
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