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參數(shù)資料
| 型號： | MC68HC05T7B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 107/109頁 |
| 文件大?。?/td> | 9008K |
| 代理商： | MC68HC05T7B |
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Computer Operating Properly Module (COP)
Interrupts
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 3.0
Technical Data
MOTOROLA
Computer Operating Properly Module (COP)
97
8.4.3 Clearing the COP Watchdog
To clear the COP watchdog and prevent a COP reset, write a logic 0 to
bit 0 (COPC) of the COP register at location $07F0 (see Figure 8-1).
Clearing the COP bit disables the COP watchdog timer regardless of the
IRQ/VPP pin voltage.
If the main program executes within the COP timeout period, the clearing
routine should be executed only once. If the main program takes longer
than the COP timeout period, the clearing routine must be executed
more than once.
NOTE:
Place the clearing routine in the main program and not in an interrupt
routine. Clearing the COP watchdog in an interrupt routine might prevent
COP watchdog timeouts even though the main program is not operating
properly.
8.5 Interrupts
The COP watchdog does not generate interrupts.
8.6 COP Register
The COP register (COPR) is a write-only register that returns the
contents of EPROM location $07F0 when read.
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $07F0
returns undefined results.
Address:
$07F0
Bit 7
6
54321
Bit 0
Read:
Write:
COPC
Reset:
UUUUUUU
0
= Unimplemented
U = Unaffected
Figure 8-1. COP Register (COPR)
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