參數(shù)資料
型號(hào)： MC68HC05T7B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝： SDIP-56
文件頁(yè)數(shù)： 7/109頁(yè)
文件大?。?/td> 9008K
代理商： MC68HC05T7B
Technical Data
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 3.0
106
External Interrupt Module (IRQ)
MOTOROLA
External Interrupt Module (IRQ)
9.6 Timing
Figure 9-5. External Interrupt Timing
Table 9-2. External Interrupt Timing (VDD = 5.0 Vdc)
(1)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to + 85°C, unless otherwise noted.
Characteristic
Symbol
Min
Max
Unit
IRQ Interrupt Pulse Width Low
(Edge-Triggered)
tILIH
1.5
—
tcyc
(2)
2.
tcyc = 1/fOP; fOP = fOSC/2.
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered)
tILIH
1.5
Note(3)
3. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19 tcyc.
tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge-Triggered)
tILIL
1.5
—
tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge- and Level-Triggered)
tILIH
1.5
Note(3)
tcyc
Table 9-3. External Interrupt Timing (VDD = 3.3 Vdc)
(1)
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to + 85°C, unless otherwise noted.
Characteristic
Symbol
Min
Max
Unit
IRQ Interrupt Pulse Width Low
(Edge-Triggered)
tILIH
1.5
—
tcyc
(2)
2.
tcyc = 1/fOP; fOP = fOSC/2.
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered)
tILIH
1.5
Note(3)
3. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19
tcyc.
tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge-Triggered)
tILIL
1.5
—
tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge- and Level-Triggered)
tILIH
1.5
Note(3)
tcyc
IRQ (INTERNAL)
tILIH
tILIL
tILIH
IRQ/VPP PIN
IRQ1
IRQn
.
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